// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Copyright (c) 2013 Linaro Ltd. * Author: Thomas Abraham <[email protected]> * * Common Clock Framework support for Exynos5250 SoC. */ #include <dt-bindings/clock/exynos5250.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include "clk.h" #include "clk-cpu.h" #include "clk-exynos5-subcmu.h" #define APLL_LOCK … #define APLL_CON0 … #define SRC_CPU … #define DIV_CPU0 … #define PWR_CTRL1 … #define PWR_CTRL2 … #define MPLL_LOCK … #define MPLL_CON0 … #define SRC_CORE1 … #define GATE_IP_ACP … #define GATE_IP_ISP0 … #define GATE_IP_ISP1 … #define CPLL_LOCK … #define EPLL_LOCK … #define VPLL_LOCK … #define GPLL_LOCK … #define CPLL_CON0 … #define EPLL_CON0 … #define VPLL_CON0 … #define GPLL_CON0 … #define SRC_TOP0 … #define SRC_TOP1 … #define SRC_TOP2 … #define SRC_TOP3 … #define SRC_GSCL … #define SRC_DISP1_0 … #define SRC_MAU … #define SRC_FSYS … #define SRC_GEN … #define SRC_PERIC0 … #define SRC_PERIC1 … #define SRC_MASK_GSCL … #define SRC_MASK_DISP1_0 … #define SRC_MASK_MAU … #define SRC_MASK_FSYS … #define SRC_MASK_GEN … #define SRC_MASK_PERIC0 … #define SRC_MASK_PERIC1 … #define DIV_TOP0 … #define DIV_TOP1 … #define DIV_GSCL … #define DIV_DISP1_0 … #define DIV_GEN … #define DIV_MAU … #define DIV_FSYS0 … #define DIV_FSYS1 … #define DIV_FSYS2 … #define DIV_PERIC0 … #define DIV_PERIC1 … #define DIV_PERIC2 … #define DIV_PERIC3 … #define DIV_PERIC4 … #define DIV_PERIC5 … #define GATE_IP_GSCL … #define GATE_IP_DISP1 … #define GATE_IP_MFC … #define GATE_IP_G3D … #define GATE_IP_GEN … #define GATE_IP_FSYS … #define GATE_IP_PERIC … #define GATE_IP_PERIS … #define BPLL_LOCK … #define BPLL_CON0 … #define SRC_CDREX … #define PLL_DIV2_SEL … /*Below definitions are used for PWR_CTRL settings*/ #define PWR_CTRL1_CORE2_DOWN_RATIO … #define PWR_CTRL1_CORE1_DOWN_RATIO … #define PWR_CTRL1_DIV2_DOWN_EN … #define PWR_CTRL1_DIV1_DOWN_EN … #define PWR_CTRL1_USE_CORE1_WFE … #define PWR_CTRL1_USE_CORE0_WFE … #define PWR_CTRL1_USE_CORE1_WFI … #define PWR_CTRL1_USE_CORE0_WFI … #define PWR_CTRL2_DIV2_UP_EN … #define PWR_CTRL2_DIV1_UP_EN … #define PWR_CTRL2_DUR_STANDBY2_VAL … #define PWR_CTRL2_DUR_STANDBY1_VAL … #define PWR_CTRL2_CORE2_UP_RATIO … #define PWR_CTRL2_CORE1_UP_RATIO … /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR … /* list of PLLs to be registered */ enum exynos5250_plls { … }; static void __iomem *reg_base; /* * list of controller registers to be saved and restored during a * suspend/resume cycle. */ static const unsigned long exynos5250_clk_regs[] __initconst = …; /* list of all parent clock list */ PNAME(mout_apll_p) = …; PNAME(mout_cpu_p) = …; PNAME(mout_mpll_fout_p) = …; PNAME(mout_mpll_p) = …; PNAME(mout_bpll_fout_p) = …; PNAME(mout_bpll_p) = …; PNAME(mout_vpllsrc_p) = …; PNAME(mout_vpll_p) = …; PNAME(mout_cpll_p) = …; PNAME(mout_epll_p) = …; PNAME(mout_gpll_p) = …; PNAME(mout_mpll_user_p) = …; PNAME(mout_bpll_user_p) = …; PNAME(mout_aclk166_p) = …; PNAME(mout_aclk200_p) = …; PNAME(mout_aclk300_p) = …; PNAME(mout_aclk400_p) = …; PNAME(mout_aclk200_sub_p) = …; PNAME(mout_aclk266_sub_p) = …; PNAME(mout_aclk300_sub_p) = …; PNAME(mout_aclk300_disp1_mid1_p) = …; PNAME(mout_aclk333_sub_p) = …; PNAME(mout_aclk400_isp_sub_p) = …; PNAME(mout_hdmi_p) = …; PNAME(mout_usb3_p) = …; PNAME(mout_group1_p) = …; PNAME(mout_audio0_p) = …; PNAME(mout_audio1_p) = …; PNAME(mout_audio2_p) = …; PNAME(mout_spdif_p) = …; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = …; /* fixed rate clocks generated inside the soc */ static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = …; static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = …; static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = …; static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = …; static const struct samsung_div_clock exynos5250_div_clks[] __initconst = …; static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = …; static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = …; static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = …; static const struct exynos5_subcmu_info exynos5250_disp_subcmu = …; static const struct exynos5_subcmu_info *exynos5250_subcmus[] = …; static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = …; static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = …; static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = …; static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = …; #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) … #define E5250_CPU_DIV1(hpm, copy) … static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = …; static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = …; static const struct of_device_id ext_clk_match[] __initconst = …; /* register exynox5250 clocks */ static void __init exynos5250_clk_init(struct device_node *np) { … } CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
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