// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Naveen Krishna Ch <[email protected]> */ #include <linux/clk-provider.h> #include <linux/of.h> #include "clk.h" #include <dt-bindings/clock/exynos7-clk.h> /* Register Offset definitions for CMU_TOPC (0x10570000) */ #define CC_PLL_LOCK … #define BUS0_PLL_LOCK … #define BUS1_DPLL_LOCK … #define MFC_PLL_LOCK … #define AUD_PLL_LOCK … #define CC_PLL_CON0 … #define BUS0_PLL_CON0 … #define BUS1_DPLL_CON0 … #define MFC_PLL_CON0 … #define AUD_PLL_CON0 … #define MUX_SEL_TOPC0 … #define MUX_SEL_TOPC1 … #define MUX_SEL_TOPC2 … #define MUX_SEL_TOPC3 … #define DIV_TOPC0 … #define DIV_TOPC1 … #define DIV_TOPC3 … #define ENABLE_ACLK_TOPC0 … #define ENABLE_ACLK_TOPC1 … #define ENABLE_SCLK_TOPC1 … static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_TOPC */ PNAME(mout_topc_aud_pll_ctrl_p) = …; PNAME(mout_topc_bus0_pll_ctrl_p) = …; PNAME(mout_topc_bus1_pll_ctrl_p) = …; PNAME(mout_topc_cc_pll_ctrl_p) = …; PNAME(mout_topc_mfc_pll_ctrl_p) = …; PNAME(mout_topc_group2) = …; PNAME(mout_topc_bus0_pll_half_p) = …; PNAME(mout_topc_bus1_pll_half_p) = …; PNAME(mout_topc_cc_pll_half_p) = …; PNAME(mout_topc_mfc_pll_half_p) = …; PNAME(mout_topc_bus0_pll_out_p) = …; static const unsigned long topc_clk_regs[] __initconst = …; static const struct samsung_mux_clock topc_mux_clks[] __initconst = …; static const struct samsung_div_clock topc_div_clks[] __initconst = …; static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = …; static const struct samsung_gate_clock topc_gate_clks[] __initconst = …; static const struct samsung_pll_clock topc_pll_clks[] __initconst = …; static const struct samsung_cmu_info topc_cmu_info __initconst = …; static void __init exynos7_clk_topc_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", exynos7_clk_topc_init); /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ #define MUX_SEL_TOP00 … #define MUX_SEL_TOP01 … #define MUX_SEL_TOP03 … #define MUX_SEL_TOP0_PERIC0 … #define MUX_SEL_TOP0_PERIC1 … #define MUX_SEL_TOP0_PERIC2 … #define MUX_SEL_TOP0_PERIC3 … #define DIV_TOP03 … #define DIV_TOP0_PERIC0 … #define DIV_TOP0_PERIC1 … #define DIV_TOP0_PERIC2 … #define DIV_TOP0_PERIC3 … #define ENABLE_ACLK_TOP03 … #define ENABLE_SCLK_TOP0_PERIC0 … #define ENABLE_SCLK_TOP0_PERIC1 … #define ENABLE_SCLK_TOP0_PERIC2 … #define ENABLE_SCLK_TOP0_PERIC3 … /* List of parent clocks for Muxes in CMU_TOP0 */ PNAME(mout_top0_bus0_pll_user_p) = …; PNAME(mout_top0_bus1_pll_user_p) = …; PNAME(mout_top0_cc_pll_user_p) = …; PNAME(mout_top0_mfc_pll_user_p) = …; PNAME(mout_top0_aud_pll_user_p) = …; PNAME(mout_top0_bus0_pll_half_p) = …; PNAME(mout_top0_bus1_pll_half_p) = …; PNAME(mout_top0_cc_pll_half_p) = …; PNAME(mout_top0_mfc_pll_half_p) = …; PNAME(mout_top0_group1) = …; PNAME(mout_top0_group3) = …; PNAME(mout_top0_group4) = …; static const unsigned long top0_clk_regs[] __initconst = …; static const struct samsung_mux_clock top0_mux_clks[] __initconst = …; static const struct samsung_div_clock top0_div_clks[] __initconst = …; static const struct samsung_gate_clock top0_gate_clks[] __initconst = …; static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = …; static const struct samsung_cmu_info top0_cmu_info __initconst = …; static void __init exynos7_clk_top0_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", exynos7_clk_top0_init); /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ #define MUX_SEL_TOP10 … #define MUX_SEL_TOP11 … #define MUX_SEL_TOP13 … #define MUX_SEL_TOP1_FSYS0 … #define MUX_SEL_TOP1_FSYS1 … #define MUX_SEL_TOP1_FSYS11 … #define DIV_TOP13 … #define DIV_TOP1_FSYS0 … #define DIV_TOP1_FSYS1 … #define DIV_TOP1_FSYS11 … #define ENABLE_ACLK_TOP13 … #define ENABLE_SCLK_TOP1_FSYS0 … #define ENABLE_SCLK_TOP1_FSYS1 … #define ENABLE_SCLK_TOP1_FSYS11 … /* List of parent clocks for Muxes in CMU_TOP1 */ PNAME(mout_top1_bus0_pll_user_p) = …; PNAME(mout_top1_bus1_pll_user_p) = …; PNAME(mout_top1_cc_pll_user_p) = …; PNAME(mout_top1_mfc_pll_user_p) = …; PNAME(mout_top1_bus0_pll_half_p) = …; PNAME(mout_top1_bus1_pll_half_p) = …; PNAME(mout_top1_cc_pll_half_p) = …; PNAME(mout_top1_mfc_pll_half_p) = …; PNAME(mout_top1_group1) = …; static const unsigned long top1_clk_regs[] __initconst = …; static const struct samsung_mux_clock top1_mux_clks[] __initconst = …; static const struct samsung_div_clock top1_div_clks[] __initconst = …; static const struct samsung_gate_clock top1_gate_clks[] __initconst = …; static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = …; static const struct samsung_cmu_info top1_cmu_info __initconst = …; static void __init exynos7_clk_top1_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", exynos7_clk_top1_init); /* Register Offset definitions for CMU_CCORE (0x105B0000) */ #define MUX_SEL_CCORE … #define DIV_CCORE … #define ENABLE_ACLK_CCORE0 … #define ENABLE_ACLK_CCORE1 … #define ENABLE_PCLK_CCORE … /* * List of parent clocks for Muxes in CMU_CCORE */ PNAME(mout_aclk_ccore_133_user_p) = …; static const unsigned long ccore_clk_regs[] __initconst = …; static const struct samsung_mux_clock ccore_mux_clks[] __initconst = …; static const struct samsung_gate_clock ccore_gate_clks[] __initconst = …; static const struct samsung_cmu_info ccore_cmu_info __initconst = …; static void __init exynos7_clk_ccore_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", exynos7_clk_ccore_init); /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ #define MUX_SEL_PERIC0 … #define ENABLE_PCLK_PERIC0 … #define ENABLE_SCLK_PERIC0 … /* List of parent clocks for Muxes in CMU_PERIC0 */ PNAME(mout_aclk_peric0_66_user_p) = …; PNAME(mout_sclk_uart0_user_p) = …; static const unsigned long peric0_clk_regs[] __initconst = …; static const struct samsung_mux_clock peric0_mux_clks[] __initconst = …; static const struct samsung_gate_clock peric0_gate_clks[] __initconst = …; static const struct samsung_cmu_info peric0_cmu_info __initconst = …; static void __init exynos7_clk_peric0_init(struct device_node *np) { … } /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ #define MUX_SEL_PERIC10 … #define MUX_SEL_PERIC11 … #define MUX_SEL_PERIC12 … #define ENABLE_PCLK_PERIC1 … #define ENABLE_SCLK_PERIC10 … CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", exynos7_clk_peric0_init); /* List of parent clocks for Muxes in CMU_PERIC1 */ PNAME(mout_aclk_peric1_66_user_p) = …; PNAME(mout_sclk_uart1_user_p) = …; PNAME(mout_sclk_uart2_user_p) = …; PNAME(mout_sclk_uart3_user_p) = …; PNAME(mout_sclk_spi0_user_p) = …; PNAME(mout_sclk_spi1_user_p) = …; PNAME(mout_sclk_spi2_user_p) = …; PNAME(mout_sclk_spi3_user_p) = …; PNAME(mout_sclk_spi4_user_p) = …; static const unsigned long peric1_clk_regs[] __initconst = …; static const struct samsung_mux_clock peric1_mux_clks[] __initconst = …; static const struct samsung_gate_clock peric1_gate_clks[] __initconst = …; static const struct samsung_cmu_info peric1_cmu_info __initconst = …; static void __init exynos7_clk_peric1_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", exynos7_clk_peric1_init); /* Register Offset definitions for CMU_PERIS (0x10040000) */ #define MUX_SEL_PERIS … #define ENABLE_PCLK_PERIS … #define ENABLE_PCLK_PERIS_SECURE_CHIPID … #define ENABLE_SCLK_PERIS … #define ENABLE_SCLK_PERIS_SECURE_CHIPID … /* List of parent clocks for Muxes in CMU_PERIS */ PNAME(mout_aclk_peris_66_user_p) = …; static const unsigned long peris_clk_regs[] __initconst = …; static const struct samsung_mux_clock peris_mux_clks[] __initconst = …; static const struct samsung_gate_clock peris_gate_clks[] __initconst = …; static const struct samsung_cmu_info peris_cmu_info __initconst = …; static void __init exynos7_clk_peris_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", exynos7_clk_peris_init); /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ #define MUX_SEL_FSYS00 … #define MUX_SEL_FSYS01 … #define MUX_SEL_FSYS02 … #define ENABLE_ACLK_FSYS00 … #define ENABLE_ACLK_FSYS01 … #define ENABLE_SCLK_FSYS01 … #define ENABLE_SCLK_FSYS02 … #define ENABLE_SCLK_FSYS04 … /* * List of parent clocks for Muxes in CMU_FSYS0 */ PNAME(mout_aclk_fsys0_200_user_p) = …; PNAME(mout_sclk_mmc2_user_p) = …; PNAME(mout_sclk_usbdrd300_user_p) = …; PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = …; PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = …; /* fixed rate clocks used in the FSYS0 block */ static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = …; static const unsigned long fsys0_clk_regs[] __initconst = …; static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = …; static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = …; static const struct samsung_cmu_info fsys0_cmu_info __initconst = …; static void __init exynos7_clk_fsys0_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", exynos7_clk_fsys0_init); /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ #define MUX_SEL_FSYS10 … #define MUX_SEL_FSYS11 … #define MUX_SEL_FSYS12 … #define DIV_FSYS1 … #define ENABLE_ACLK_FSYS1 … #define ENABLE_PCLK_FSYS1 … #define ENABLE_SCLK_FSYS11 … #define ENABLE_SCLK_FSYS12 … #define ENABLE_SCLK_FSYS13 … /* * List of parent clocks for Muxes in CMU_FSYS1 */ PNAME(mout_aclk_fsys1_200_user_p) = …; PNAME(mout_fsys1_group_p) = …; PNAME(mout_sclk_mmc0_user_p) = …; PNAME(mout_sclk_mmc1_user_p) = …; PNAME(mout_sclk_ufsunipro20_user_p) = …; PNAME(mout_phyclk_ufs20_tx0_user_p) = …; PNAME(mout_phyclk_ufs20_rx0_user_p) = …; PNAME(mout_phyclk_ufs20_rx1_user_p) = …; /* fixed rate clocks used in the FSYS1 block */ static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = …; static const unsigned long fsys1_clk_regs[] __initconst = …; static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = …; static const struct samsung_div_clock fsys1_div_clks[] __initconst = …; static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = …; static const struct samsung_cmu_info fsys1_cmu_info __initconst = …; static void __init exynos7_clk_fsys1_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", exynos7_clk_fsys1_init); #define MUX_SEL_MSCL … #define DIV_MSCL … #define ENABLE_ACLK_MSCL … #define ENABLE_PCLK_MSCL … /* List of parent clocks for Muxes in CMU_MSCL */ PNAME(mout_aclk_mscl_532_user_p) = …; static const unsigned long mscl_clk_regs[] __initconst = …; static const struct samsung_mux_clock mscl_mux_clks[] __initconst = …; static const struct samsung_div_clock mscl_div_clks[] __initconst = …; static const struct samsung_gate_clock mscl_gate_clks[] __initconst = …; static const struct samsung_cmu_info mscl_cmu_info __initconst = …; static void __init exynos7_clk_mscl_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", exynos7_clk_mscl_init); /* Register Offset definitions for CMU_AUD (0x114C0000) */ #define MUX_SEL_AUD … #define DIV_AUD0 … #define DIV_AUD1 … #define ENABLE_ACLK_AUD … #define ENABLE_PCLK_AUD … #define ENABLE_SCLK_AUD … /* * List of parent clocks for Muxes in CMU_AUD */ PNAME(mout_aud_pll_user_p) = …; PNAME(mout_aud_group_p) = …; static const unsigned long aud_clk_regs[] __initconst = …; static const struct samsung_mux_clock aud_mux_clks[] __initconst = …; static const struct samsung_div_clock aud_div_clks[] __initconst = …; static const struct samsung_gate_clock aud_gate_clks[] __initconst = …; static const struct samsung_cmu_info aud_cmu_info __initconst = …; static void __init exynos7_clk_aud_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", exynos7_clk_aud_init);
Codebase Browser
linux