linux/sound/soc/mediatek/mt8195/mt8195-afe-clk.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * mt8195-afe-clk.h  --  Mediatek 8195 afe clock ctrl definition
 *
 * Copyright (c) 2021 MediaTek Inc.
 * Author: Bicycle Tsai <[email protected]>
 *         Trevor Wu <[email protected]>
 */

#ifndef _MT8195_AFE_CLK_H_
#define _MT8195_AFE_CLK_H_

enum { … };

enum { … };

enum { … };

struct mtk_base_afe;

int mt8195_afe_get_mclk_source_clk_id(int sel);
int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
int mt8195_afe_get_default_mclk_source_by_rate(int rate);
int mt8195_afe_init_clock(struct mtk_base_afe *afe);
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
			    unsigned int rate);
int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
			      struct clk *parent);
int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe);
int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe);
int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);

#endif