// SPDX-License-Identifier: GPL-2.0 /* * MediaTek ALSA SoC AFE platform driver for 8188 * * Copyright (c) 2022 MediaTek Inc. * Author: Bicycle Tsai <[email protected]> * Trevor Wu <[email protected]> * Chun-Chia Chiu <[email protected]> */ #include <linux/arm-smccc.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/module.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/of_reserved_mem.h> #include <linux/pm_runtime.h> #include <linux/soc/mediatek/infracfg.h> #include <linux/reset.h> #include <sound/pcm_params.h> #include "mt8188-afe-common.h" #include "mt8188-afe-clk.h" #include "mt8188-reg.h" #include "../common/mtk-afe-platform-driver.h" #include "../common/mtk-afe-fe-dai.h" #define MT8188_MEMIF_BUFFER_BYTES_ALIGN … #define MT8188_MEMIF_DL7_MAX_PERIOD_SIZE … #define MEMIF_AXI_MINLEN … struct mtk_dai_memif_priv { … }; static const struct snd_pcm_hardware mt8188_afe_hardware = …; struct mt8188_afe_rate { … }; static const struct mt8188_afe_rate mt8188_afe_rates[] = …; int mt8188_afe_fs_timing(unsigned int rate) { … } static int mt8188_memif_fs(struct snd_pcm_substream *substream, unsigned int rate) { … } static int mt8188_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) { … } enum { … }; struct mt8188_afe_channel_merge { … }; static const struct mt8188_afe_channel_merge mt8188_afe_cm[MT8188_AFE_CM_NUM] = …; static int mt8188_afe_memif_is_ul(int id) { … } static const struct mt8188_afe_channel_merge * mt8188_afe_found_cm(struct snd_soc_dai *dai) { … } static int mt8188_afe_config_cm(struct mtk_base_afe *afe, const struct mt8188_afe_channel_merge *cm, unsigned int channels) { … } static int mt8188_afe_enable_cm(struct mtk_base_afe *afe, const struct mt8188_afe_channel_merge *cm, bool enable) { … } static int mt8188_afe_fe_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static void mt8188_afe_fe_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { … } static int mt8188_afe_fe_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { … } static int mt8188_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { … } static const struct snd_soc_dai_ops mt8188_afe_fe_dai_ops = …; #define MTK_PCM_RATES … #define MTK_PCM_FORMATS … static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = …; static const struct snd_kcontrol_new o002_mix[] = …; static const struct snd_kcontrol_new o003_mix[] = …; static const struct snd_kcontrol_new o004_mix[] = …; static const struct snd_kcontrol_new o005_mix[] = …; static const struct snd_kcontrol_new o006_mix[] = …; static const struct snd_kcontrol_new o007_mix[] = …; static const struct snd_kcontrol_new o008_mix[] = …; static const struct snd_kcontrol_new o009_mix[] = …; static const struct snd_kcontrol_new o010_mix[] = …; static const struct snd_kcontrol_new o011_mix[] = …; static const struct snd_kcontrol_new o012_mix[] = …; static const struct snd_kcontrol_new o013_mix[] = …; static const struct snd_kcontrol_new o014_mix[] = …; static const struct snd_kcontrol_new o015_mix[] = …; static const struct snd_kcontrol_new o016_mix[] = …; static const struct snd_kcontrol_new o017_mix[] = …; static const struct snd_kcontrol_new o018_mix[] = …; static const struct snd_kcontrol_new o019_mix[] = …; static const struct snd_kcontrol_new o020_mix[] = …; static const struct snd_kcontrol_new o021_mix[] = …; static const struct snd_kcontrol_new o022_mix[] = …; static const struct snd_kcontrol_new o023_mix[] = …; static const struct snd_kcontrol_new o024_mix[] = …; static const struct snd_kcontrol_new o025_mix[] = …; static const struct snd_kcontrol_new o026_mix[] = …; static const struct snd_kcontrol_new o027_mix[] = …; static const struct snd_kcontrol_new o028_mix[] = …; static const struct snd_kcontrol_new o029_mix[] = …; static const struct snd_kcontrol_new o030_mix[] = …; static const struct snd_kcontrol_new o031_mix[] = …; static const struct snd_kcontrol_new o032_mix[] = …; static const struct snd_kcontrol_new o033_mix[] = …; static const struct snd_kcontrol_new o034_mix[] = …; static const struct snd_kcontrol_new o035_mix[] = …; static const struct snd_kcontrol_new o036_mix[] = …; static const struct snd_kcontrol_new o037_mix[] = …; static const struct snd_kcontrol_new o038_mix[] = …; static const struct snd_kcontrol_new o039_mix[] = …; static const struct snd_kcontrol_new o040_mix[] = …; static const struct snd_kcontrol_new o041_mix[] = …; static const struct snd_kcontrol_new o042_mix[] = …; static const struct snd_kcontrol_new o043_mix[] = …; static const struct snd_kcontrol_new o044_mix[] = …; static const struct snd_kcontrol_new o045_mix[] = …; static const struct snd_kcontrol_new o046_mix[] = …; static const struct snd_kcontrol_new o047_mix[] = …; static const struct snd_kcontrol_new o182_mix[] = …; static const struct snd_kcontrol_new o183_mix[] = …; static const char * const dl8_dl11_data_sel_mux_text[] = …; static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum, AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text); static const struct snd_kcontrol_new dl8_dl11_data_sel_mux = …; static const struct snd_soc_dapm_widget mt8188_memif_widgets[] = …; static const struct snd_soc_dapm_route mt8188_memif_routes[] = …; static const char * const mt8188_afe_1x_en_sel_text[] = …; static const unsigned int mt8188_afe_1x_en_sel_values[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum, A3_A4_TIMING_SEL1, 18, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum, A3_A4_TIMING_SEL1, 20, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum, A3_A4_TIMING_SEL1, 22, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum, A3_A4_TIMING_SEL1, 24, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum, A3_A4_TIMING_SEL1, 26, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum, A3_A4_TIMING_SEL1, 28, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum, A3_A4_TIMING_SEL1, 30, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum, A3_A4_TIMING_SEL1, 0, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum, A3_A4_TIMING_SEL1, 2, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum, A3_A4_TIMING_SEL1, 4, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum, A3_A4_TIMING_SEL1, 6, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum, A3_A4_TIMING_SEL1, 8, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum, A3_A4_TIMING_SEL1, 10, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum, A3_A4_TIMING_SEL1, 12, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum, A3_A4_TIMING_SEL1, 14, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum, A3_A4_TIMING_SEL1, 16, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum, A3_A4_TIMING_SEL6, 0, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum, A3_A4_TIMING_SEL6, 2, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum, A3_A4_TIMING_SEL6, 4, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum, A3_A4_TIMING_SEL6, 6, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum, A3_A4_TIMING_SEL6, 8, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum, A3_A4_TIMING_SEL6, 10, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum, A3_A4_TIMING_SEL6, 12, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum, A3_A4_TIMING_SEL6, 14, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum, A3_A4_TIMING_SEL6, 16, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum, A3_A4_TIMING_SEL6, 18, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum, A3_A4_TIMING_SEL6, 20, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum, A3_A4_TIMING_SEL6, 22, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum, A3_A4_TIMING_SEL6, 24, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum, A3_A4_TIMING_SEL6, 26, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum, A3_A4_TIMING_SEL6, 28, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum, A3_A4_TIMING_SEL6, 30, 0x3, mt8188_afe_1x_en_sel_text, mt8188_afe_1x_en_sel_values); static const char * const mt8188_afe_fs_timing_sel_text[] = …; static const unsigned int mt8188_afe_fs_timing_sel_values[] = …; static SOC_VALUE_ENUM_SINGLE_DECL(dl2_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl3_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl6_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl8_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(dl11_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul2_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul4_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul5_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul9_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static SOC_VALUE_ENUM_SINGLE_DECL(ul10_fs_timing_sel_enum, SND_SOC_NOPM, 0, 0, mt8188_afe_fs_timing_sel_text, mt8188_afe_fs_timing_sel_values); static int mt8188_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int mt8188_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int mt8188_memif_fs_timing_sel_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static int mt8188_memif_fs_timing_sel_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { … } static const struct snd_kcontrol_new mt8188_memif_controls[] = …; static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = …; static const struct mtk_base_irq_data irq_data[MT8188_AFE_IRQ_NUM] = …; static const int mt8188_afe_memif_const_irqs[MT8188_AFE_MEMIF_NUM] = …; static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg) { … } static const struct regmap_config mt8188_afe_regmap_config = …; #define AFE_IRQ_CLR_BITS … #define ASYS_IRQ_CLR_BITS … static irqreturn_t mt8188_afe_irq_handler(int irq_id, void *dev_id) { … } static int mt8188_afe_runtime_suspend(struct device *dev) { … } static int mt8188_afe_runtime_resume(struct device *dev) { … } static int init_memif_priv_data(struct mtk_base_afe *afe) { … } static int mt8188_dai_memif_register(struct mtk_base_afe *afe) { … } dai_register_cb; static const dai_register_cb dai_register_cbs[] = …; static const struct reg_sequence mt8188_afe_reg_defaults[] = …; static const struct reg_sequence mt8188_cg_patch[] = …; static int mt8188_afe_init_registers(struct mtk_base_afe *afe) { … } static int mt8188_afe_parse_of(struct mtk_base_afe *afe, struct device_node *np) { … } #define MT8188_DELAY_US … #define MT8188_TIMEOUT_US … static int bus_protect_enable(struct regmap *regmap) { … } static int bus_protect_disable(struct regmap *regmap) { … } static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev) { … } static const struct of_device_id mt8188_afe_pcm_dt_match[] = …; MODULE_DEVICE_TABLE(of, mt8188_afe_pcm_dt_match); static const struct dev_pm_ops mt8188_afe_pm_ops = …; static struct platform_driver mt8188_afe_pcm_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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