/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __Q6AFE_H__ #define __Q6AFE_H__ #define AFE_PORT_MAX … #define MSM_AFE_PORT_TYPE_RX … #define MSM_AFE_PORT_TYPE_TX … #define AFE_MAX_PORTS … #define Q6AFE_MAX_MI2S_LINES … #define AFE_MAX_CHAN_COUNT … #define AFE_PORT_MAX_AUDIO_CHAN_CNT … #define Q6AFE_LPASS_CLK_SRC_INTERNAL … #define Q6AFE_LPASS_CLK_ROOT_DEFAULT … #define LPAIF_DIG_CLK … #define LPAIF_BIT_CLK … #define LPAIF_OSR_CLK … /* Clock ID for Primary I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT … /* Clock ID for Primary I2S EBIT */ #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT … /* Clock ID for Secondary I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT … /* Clock ID for Secondary I2S EBIT */ #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT … /* Clock ID for Tertiary I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT … /* Clock ID for Tertiary I2S EBIT */ #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT … /* Clock ID for Quartnery I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT … /* Clock ID for Quartnery I2S EBIT */ #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT … /* Clock ID for Speaker I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT … /* Clock ID for Speaker I2S EBIT */ #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT … /* Clock ID for Speaker I2S OSR */ #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR … /* Clock ID for QUINARY I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT … /* Clock ID for QUINARY I2S EBIT */ #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT … /* Clock ID for SENARY I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT … /* Clock ID for SENARY I2S EBIT */ #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT … /* Clock ID for INT0 I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT … /* Clock ID for INT1 I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT … /* Clock ID for INT2 I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT … /* Clock ID for INT3 I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT … /* Clock ID for INT4 I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT … /* Clock ID for INT5 I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT … /* Clock ID for INT6 I2S IBIT */ #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT … /* Clock ID for QUINARY MI2S OSR CLK */ #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR … /* Clock ID for Primary PCM IBIT */ #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT … /* Clock ID for Primary PCM EBIT */ #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT … /* Clock ID for Secondary PCM IBIT */ #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT … /* Clock ID for Secondary PCM EBIT */ #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT … /* Clock ID for Tertiary PCM IBIT */ #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT … /* Clock ID for Tertiary PCM EBIT */ #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT … /* Clock ID for Quartery PCM IBIT */ #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT … /* Clock ID for Quartery PCM EBIT */ #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT … /* Clock ID for Quinary PCM IBIT */ #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT … /* Clock ID for Quinary PCM EBIT */ #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT … /* Clock ID for QUINARY PCM OSR */ #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR … /** Clock ID for Primary TDM IBIT */ #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT … /** Clock ID for Primary TDM EBIT */ #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT … /** Clock ID for Secondary TDM IBIT */ #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT … /** Clock ID for Secondary TDM EBIT */ #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT … /** Clock ID for Tertiary TDM IBIT */ #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT … /** Clock ID for Tertiary TDM EBIT */ #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT … /** Clock ID for Quartery TDM IBIT */ #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT … /** Clock ID for Quartery TDM EBIT */ #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT … /** Clock ID for Quinary TDM IBIT */ #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT … /** Clock ID for Quinary TDM EBIT */ #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT … /** Clock ID for Quinary TDM OSR */ #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR … /* Clock ID for MCLK1 */ #define Q6AFE_LPASS_CLK_ID_MCLK_1 … /* Clock ID for MCLK2 */ #define Q6AFE_LPASS_CLK_ID_MCLK_2 … /* Clock ID for MCLK3 */ #define Q6AFE_LPASS_CLK_ID_MCLK_3 … /* Clock ID for MCLK4 */ #define Q6AFE_LPASS_CLK_ID_MCLK_4 … /* Clock ID for Internal Digital Codec Core */ #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE … /* Clock ID for INT MCLK0 */ #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 … /* Clock ID for INT MCLK1 */ #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 … #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK … #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK … #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK … #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK … #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK … #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK … #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK … #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK … #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK … #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK … #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK … /* Clock attribute for invalid use (reserved for internal usage) */ #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID … /* Clock attribute for no couple case */ #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO … /* Clock attribute for dividend couple case */ #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND … /* Clock attribute for divisor couple case */ #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR … /* Clock attribute for invert and no couple case */ #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO … #define Q6AFE_CMAP_INVALID … struct q6afe_hdmi_cfg { … }; struct q6afe_slim_cfg { … }; struct q6afe_i2s_cfg { … }; struct q6afe_tdm_cfg { … }; struct q6afe_cdc_dma_cfg { … }; struct q6afe_port_config { … }; struct q6afe_port; struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id); int q6afe_port_start(struct q6afe_port *port); int q6afe_port_stop(struct q6afe_port *port); void q6afe_port_put(struct q6afe_port *port); int q6afe_get_port_id(int index); void q6afe_hdmi_port_prepare(struct q6afe_port *port, struct q6afe_hdmi_cfg *cfg); void q6afe_slim_port_prepare(struct q6afe_port *port, struct q6afe_slim_cfg *cfg); int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg); void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg); void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, struct q6afe_cdc_dma_cfg *cfg); int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, int clk_src, int clk_root, unsigned int freq, int dir); int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, int clk_root, unsigned int freq); int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, const char *client_name, uint32_t *client_handle); int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, uint32_t client_handle); #endif /* __Q6AFE_H__ */
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