// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. // Copyright (c) 2018, Linaro Limited #include <dt-bindings/sound/qcom,q6afe.h> #include <linux/slab.h> #include <linux/kernel.h> #include <linux/uaccess.h> #include <linux/wait.h> #include <linux/jiffies.h> #include <linux/sched.h> #include <linux/module.h> #include <linux/kref.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/spinlock.h> #include <linux/delay.h> #include <linux/soc/qcom/apr.h> #include <sound/soc.h> #include <sound/soc-dai.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include "q6dsp-errno.h" #include "q6core.h" #include "q6afe.h" /* AFE CMDs */ #define AFE_PORT_CMD_DEVICE_START … #define AFE_PORT_CMD_DEVICE_STOP … #define AFE_PORT_CMD_SET_PARAM_V2 … #define AFE_SVC_CMD_SET_PARAM … #define AFE_PORT_CMDRSP_GET_PARAM_V2 … #define AFE_PARAM_ID_HDMI_CONFIG … #define AFE_MODULE_AUDIO_DEV_INTERFACE … #define AFE_MODULE_TDM … #define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG … #define AFE_PARAM_ID_LPAIF_CLK_CONFIG … #define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG … #define AFE_PARAM_ID_SLIMBUS_CONFIG … #define AFE_PARAM_ID_I2S_CONFIG … #define AFE_PARAM_ID_TDM_CONFIG … #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG … #define AFE_PARAM_ID_CODEC_DMA_CONFIG … #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST … #define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST … #define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST … /* I2S config specific */ #define AFE_API_VERSION_I2S_CONFIG … #define AFE_PORT_I2S_SD0 … #define AFE_PORT_I2S_SD1 … #define AFE_PORT_I2S_SD2 … #define AFE_PORT_I2S_SD3 … #define AFE_PORT_I2S_SD0_MASK … #define AFE_PORT_I2S_SD1_MASK … #define AFE_PORT_I2S_SD2_MASK … #define AFE_PORT_I2S_SD3_MASK … #define AFE_PORT_I2S_SD0_1_MASK … #define AFE_PORT_I2S_SD2_3_MASK … #define AFE_PORT_I2S_SD0_1_2_MASK … #define AFE_PORT_I2S_SD0_1_2_3_MASK … #define AFE_PORT_I2S_QUAD01 … #define AFE_PORT_I2S_QUAD23 … #define AFE_PORT_I2S_6CHS … #define AFE_PORT_I2S_8CHS … #define AFE_PORT_I2S_MONO … #define AFE_PORT_I2S_STEREO … #define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL … #define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL … #define AFE_LINEAR_PCM_DATA … /* Port IDs */ #define AFE_API_VERSION_HDMI_CONFIG … #define AFE_PORT_ID_MULTICHAN_HDMI_RX … #define AFE_PORT_ID_HDMI_OVER_DP_RX … #define AFE_API_VERSION_SLIMBUS_CONFIG … /* Clock set API version */ #define AFE_API_VERSION_CLOCK_SET … #define Q6AFE_LPASS_CLK_CONFIG_API_VERSION … #define AFE_MODULE_CLOCK_SET … #define AFE_PARAM_ID_CLOCK_SET … /* SLIMbus Rx port on channel 0. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX … /* SLIMbus Tx port on channel 0. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX … /* SLIMbus Rx port on channel 1. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX … /* SLIMbus Tx port on channel 1. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX … /* SLIMbus Rx port on channel 2. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX … /* SLIMbus Tx port on channel 2. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX … /* SLIMbus Rx port on channel 3. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX … /* SLIMbus Tx port on channel 3. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX … /* SLIMbus Rx port on channel 4. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX … /* SLIMbus Tx port on channel 4. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX … /* SLIMbus Rx port on channel 5. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX … /* SLIMbus Tx port on channel 5. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX … /* SLIMbus Rx port on channel 6. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX … /* SLIMbus Tx port on channel 6. */ #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX … #define AFE_PORT_ID_PRIMARY_MI2S_RX … #define AFE_PORT_ID_PRIMARY_MI2S_TX … #define AFE_PORT_ID_SECONDARY_MI2S_RX … #define AFE_PORT_ID_SECONDARY_MI2S_TX … #define AFE_PORT_ID_TERTIARY_MI2S_RX … #define AFE_PORT_ID_TERTIARY_MI2S_TX … #define AFE_PORT_ID_QUATERNARY_MI2S_RX … #define AFE_PORT_ID_QUATERNARY_MI2S_TX … #define AFE_PORT_ID_QUINARY_MI2S_RX … #define AFE_PORT_ID_QUINARY_MI2S_TX … /* Start of the range of port IDs for TDM devices. */ #define AFE_PORT_ID_TDM_PORT_RANGE_START … /* End of the range of port IDs for TDM devices. */ #define AFE_PORT_ID_TDM_PORT_RANGE_END … /* Size of the range of port IDs for TDM ports. */ #define AFE_PORT_ID_TDM_PORT_RANGE_SIZE … #define AFE_PORT_ID_PRIMARY_TDM_RX … #define AFE_PORT_ID_PRIMARY_TDM_RX_1 … #define AFE_PORT_ID_PRIMARY_TDM_RX_2 … #define AFE_PORT_ID_PRIMARY_TDM_RX_3 … #define AFE_PORT_ID_PRIMARY_TDM_RX_4 … #define AFE_PORT_ID_PRIMARY_TDM_RX_5 … #define AFE_PORT_ID_PRIMARY_TDM_RX_6 … #define AFE_PORT_ID_PRIMARY_TDM_RX_7 … #define AFE_PORT_ID_PRIMARY_TDM_TX … #define AFE_PORT_ID_PRIMARY_TDM_TX_1 … #define AFE_PORT_ID_PRIMARY_TDM_TX_2 … #define AFE_PORT_ID_PRIMARY_TDM_TX_3 … #define AFE_PORT_ID_PRIMARY_TDM_TX_4 … #define AFE_PORT_ID_PRIMARY_TDM_TX_5 … #define AFE_PORT_ID_PRIMARY_TDM_TX_6 … #define AFE_PORT_ID_PRIMARY_TDM_TX_7 … #define AFE_PORT_ID_SECONDARY_TDM_RX … #define AFE_PORT_ID_SECONDARY_TDM_RX_1 … #define AFE_PORT_ID_SECONDARY_TDM_RX_2 … #define AFE_PORT_ID_SECONDARY_TDM_RX_3 … #define AFE_PORT_ID_SECONDARY_TDM_RX_4 … #define AFE_PORT_ID_SECONDARY_TDM_RX_5 … #define AFE_PORT_ID_SECONDARY_TDM_RX_6 … #define AFE_PORT_ID_SECONDARY_TDM_RX_7 … #define AFE_PORT_ID_SECONDARY_TDM_TX … #define AFE_PORT_ID_SECONDARY_TDM_TX_1 … #define AFE_PORT_ID_SECONDARY_TDM_TX_2 … #define AFE_PORT_ID_SECONDARY_TDM_TX_3 … #define AFE_PORT_ID_SECONDARY_TDM_TX_4 … #define AFE_PORT_ID_SECONDARY_TDM_TX_5 … #define AFE_PORT_ID_SECONDARY_TDM_TX_6 … #define AFE_PORT_ID_SECONDARY_TDM_TX_7 … #define AFE_PORT_ID_TERTIARY_TDM_RX … #define AFE_PORT_ID_TERTIARY_TDM_RX_1 … #define AFE_PORT_ID_TERTIARY_TDM_RX_2 … #define AFE_PORT_ID_TERTIARY_TDM_RX_3 … #define AFE_PORT_ID_TERTIARY_TDM_RX_4 … #define AFE_PORT_ID_TERTIARY_TDM_RX_5 … #define AFE_PORT_ID_TERTIARY_TDM_RX_6 … #define AFE_PORT_ID_TERTIARY_TDM_RX_7 … #define AFE_PORT_ID_TERTIARY_TDM_TX … #define AFE_PORT_ID_TERTIARY_TDM_TX_1 … #define AFE_PORT_ID_TERTIARY_TDM_TX_2 … #define AFE_PORT_ID_TERTIARY_TDM_TX_3 … #define AFE_PORT_ID_TERTIARY_TDM_TX_4 … #define AFE_PORT_ID_TERTIARY_TDM_TX_5 … #define AFE_PORT_ID_TERTIARY_TDM_TX_6 … #define AFE_PORT_ID_TERTIARY_TDM_TX_7 … #define AFE_PORT_ID_QUATERNARY_TDM_RX … #define AFE_PORT_ID_QUATERNARY_TDM_RX_1 … #define AFE_PORT_ID_QUATERNARY_TDM_RX_2 … #define AFE_PORT_ID_QUATERNARY_TDM_RX_3 … #define AFE_PORT_ID_QUATERNARY_TDM_RX_4 … #define AFE_PORT_ID_QUATERNARY_TDM_RX_5 … #define AFE_PORT_ID_QUATERNARY_TDM_RX_6 … #define AFE_PORT_ID_QUATERNARY_TDM_RX_7 … #define AFE_PORT_ID_QUATERNARY_TDM_TX … #define AFE_PORT_ID_QUATERNARY_TDM_TX_1 … #define AFE_PORT_ID_QUATERNARY_TDM_TX_2 … #define AFE_PORT_ID_QUATERNARY_TDM_TX_3 … #define AFE_PORT_ID_QUATERNARY_TDM_TX_4 … #define AFE_PORT_ID_QUATERNARY_TDM_TX_5 … #define AFE_PORT_ID_QUATERNARY_TDM_TX_6 … #define AFE_PORT_ID_QUATERNARY_TDM_TX_7 … #define AFE_PORT_ID_QUINARY_TDM_RX … #define AFE_PORT_ID_QUINARY_TDM_RX_1 … #define AFE_PORT_ID_QUINARY_TDM_RX_2 … #define AFE_PORT_ID_QUINARY_TDM_RX_3 … #define AFE_PORT_ID_QUINARY_TDM_RX_4 … #define AFE_PORT_ID_QUINARY_TDM_RX_5 … #define AFE_PORT_ID_QUINARY_TDM_RX_6 … #define AFE_PORT_ID_QUINARY_TDM_RX_7 … #define AFE_PORT_ID_QUINARY_TDM_TX … #define AFE_PORT_ID_QUINARY_TDM_TX_1 … #define AFE_PORT_ID_QUINARY_TDM_TX_2 … #define AFE_PORT_ID_QUINARY_TDM_TX_3 … #define AFE_PORT_ID_QUINARY_TDM_TX_4 … #define AFE_PORT_ID_QUINARY_TDM_TX_5 … #define AFE_PORT_ID_QUINARY_TDM_TX_6 … #define AFE_PORT_ID_QUINARY_TDM_TX_7 … /* AFE WSA Codec DMA Rx port 0 */ #define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 … /* AFE WSA Codec DMA Tx port 0 */ #define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 … /* AFE WSA Codec DMA Rx port 1 */ #define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 … /* AFE WSA Codec DMA Tx port 1 */ #define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 … /* AFE WSA Codec DMA Tx port 2 */ #define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 … /* AFE VA Codec DMA Tx port 0 */ #define AFE_PORT_ID_VA_CODEC_DMA_TX_0 … /* AFE VA Codec DMA Tx port 1 */ #define AFE_PORT_ID_VA_CODEC_DMA_TX_1 … /* AFE VA Codec DMA Tx port 2 */ #define AFE_PORT_ID_VA_CODEC_DMA_TX_2 … /* AFE Rx Codec DMA Rx port 0 */ #define AFE_PORT_ID_RX_CODEC_DMA_RX_0 … /* AFE Tx Codec DMA Tx port 0 */ #define AFE_PORT_ID_TX_CODEC_DMA_TX_0 … /* AFE Rx Codec DMA Rx port 1 */ #define AFE_PORT_ID_RX_CODEC_DMA_RX_1 … /* AFE Tx Codec DMA Tx port 1 */ #define AFE_PORT_ID_TX_CODEC_DMA_TX_1 … /* AFE Rx Codec DMA Rx port 2 */ #define AFE_PORT_ID_RX_CODEC_DMA_RX_2 … /* AFE Tx Codec DMA Tx port 2 */ #define AFE_PORT_ID_TX_CODEC_DMA_TX_2 … /* AFE Rx Codec DMA Rx port 3 */ #define AFE_PORT_ID_RX_CODEC_DMA_RX_3 … /* AFE Tx Codec DMA Tx port 3 */ #define AFE_PORT_ID_TX_CODEC_DMA_TX_3 … /* AFE Rx Codec DMA Rx port 4 */ #define AFE_PORT_ID_RX_CODEC_DMA_RX_4 … /* AFE Tx Codec DMA Tx port 4 */ #define AFE_PORT_ID_TX_CODEC_DMA_TX_4 … /* AFE Rx Codec DMA Rx port 5 */ #define AFE_PORT_ID_RX_CODEC_DMA_RX_5 … /* AFE Tx Codec DMA Tx port 5 */ #define AFE_PORT_ID_TX_CODEC_DMA_TX_5 … /* AFE Rx Codec DMA Rx port 6 */ #define AFE_PORT_ID_RX_CODEC_DMA_RX_6 … /* AFE Rx Codec DMA Rx port 7 */ #define AFE_PORT_ID_RX_CODEC_DMA_RX_7 … #define Q6AFE_LPASS_MODE_CLK1_VALID … #define Q6AFE_LPASS_MODE_CLK2_VALID … #define Q6AFE_LPASS_CLK_SRC_INTERNAL … #define Q6AFE_LPASS_CLK_ROOT_DEFAULT … #define AFE_API_VERSION_TDM_CONFIG … #define AFE_API_VERSION_SLOT_MAPPING_CONFIG … #define AFE_API_VERSION_CODEC_DMA_CONFIG … #define TIMEOUT_MS … #define AFE_CMD_RESP_AVAIL … #define AFE_CMD_RESP_NONE … #define AFE_CLK_TOKEN … struct q6afe { … }; struct afe_port_cmd_device_start { … } __packed; struct afe_port_cmd_device_stop { … } __packed; struct afe_port_param_data_v2 { … } __packed; struct afe_svc_cmd_set_param { … } __packed; struct afe_port_cmd_set_param_v2 { … } __packed; struct afe_param_id_hdmi_multi_chan_audio_cfg { … } __packed; struct afe_param_id_slimbus_cfg { … } __packed; struct afe_clk_cfg { … } __packed; struct afe_digital_clk_cfg { … } __packed; struct afe_param_id_i2s_cfg { … } __packed; struct afe_param_id_tdm_cfg { … } __packed; struct afe_param_id_cdc_dma_cfg { … } __packed; afe_port_config __packed; struct afe_clk_set { … }; struct afe_param_id_slot_mapping_cfg { … } __packed; struct q6afe_port { … }; struct afe_cmd_remote_lpass_core_hw_vote_request { … } __packed; struct afe_cmd_remote_lpass_core_hw_devote_request { … } __packed; struct afe_port_map { … }; /* * Mapping between Virtual Port IDs to DSP AFE Port ID * On B Family SoCs DSP Port IDs are consistent across multiple SoCs * on A Family SoCs DSP port IDs are same as virtual Port IDs. */ static struct afe_port_map port_maps[AFE_PORT_MAX] = …; static void q6afe_port_free(struct kref *ref) { … } static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token) { … } static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data) { … } /** * q6afe_get_port_id() - Get port id from a given port index * * @index: port index * * Return: Will be an negative on error or valid port_id on success */ int q6afe_get_port_id(int index) { … } EXPORT_SYMBOL_GPL(…); static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, struct q6afe_port *port, uint32_t rsp_opcode) { … } static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port, void *data, int param_id, int module_id, int psize, int token) { … } static int q6afe_port_set_param(struct q6afe_port *port, void *data, int param_id, int module_id, int psize) { … } static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, int param_id, int module_id, int psize) { … } static int q6afe_port_set_lpass_clock(struct q6afe_port *port, struct afe_clk_cfg *cfg) { … } static int q6afe_set_lpass_clock_v2(struct q6afe_port *port, struct afe_clk_set *cfg) { … } static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port, struct afe_digital_clk_cfg *cfg) { … } int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, int clk_root, unsigned int freq) { … } EXPORT_SYMBOL_GPL(…); int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, int clk_src, int clk_root, unsigned int freq, int dir) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_port_stop() - Stop a afe port * * @port: Instance of port to stop * * Return: Will be an negative on packet size on success. */ int q6afe_port_stop(struct q6afe_port *port) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_slim_port_prepare() - Prepare slim afe port. * * @port: Instance of afe port * @cfg: SLIM configuration for the afe port * */ void q6afe_slim_port_prepare(struct q6afe_port *port, struct q6afe_slim_cfg *cfg) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_tdm_port_prepare() - Prepare tdm afe port. * * @port: Instance of afe port * @cfg: TDM configuration for the afe port * */ void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_hdmi_port_prepare() - Prepare hdmi afe port. * * @port: Instance of afe port * @cfg: HDMI configuration for the afe port * */ void q6afe_hdmi_port_prepare(struct q6afe_port *port, struct q6afe_hdmi_cfg *cfg) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_i2s_port_prepare() - Prepare i2s afe port. * * @port: Instance of afe port * @cfg: I2S configuration for the afe port * Return: Will be an negative on error and zero on success. */ int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_cdc_dma_port_prepare() - Prepare dma afe port. * * @port: Instance of afe port * @cfg: DMA configuration for the afe port * */ void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, struct q6afe_cdc_dma_cfg *cfg) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_port_start() - Start a afe port * * @port: Instance of port to start * * Return: Will be an negative on packet size on success. */ int q6afe_port_start(struct q6afe_port *port) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_port_get_from_id() - Get port instance from a port id * * @dev: Pointer to afe child device. * @id: port id * * Return: Will be an error pointer on error or a valid afe port * on success. */ struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) { … } EXPORT_SYMBOL_GPL(…); /** * q6afe_port_put() - Release port reference * * @port: Instance of port to put */ void q6afe_port_put(struct q6afe_port *port) { … } EXPORT_SYMBOL_GPL(…); int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, uint32_t client_handle) { … } EXPORT_SYMBOL(…); int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, const char *client_name, uint32_t *client_handle) { … } EXPORT_SYMBOL(…); static int q6afe_probe(struct apr_device *adev) { … } #ifdef CONFIG_OF static const struct of_device_id q6afe_device_id[] = …; MODULE_DEVICE_TABLE(of, q6afe_device_id); #endif static struct apr_driver qcom_q6afe_driver = …; module_apr_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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