/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * Copyright(c) 2017 Intel Corporation * * Author: Liam Girdwood <[email protected]> */ #ifndef __SOF_INTEL_SHIM_H #define __SOF_INTEL_SHIM_H enum sof_intel_hw_ip_version { … }; /* * SHIM registers for BYT, BSW, CHT, BDW */ #define SHIM_CSR … #define SHIM_PISR … #define SHIM_PIMR … #define SHIM_ISRX … #define SHIM_ISRD … #define SHIM_IMRX … #define SHIM_IMRD … #define SHIM_IPCX … #define SHIM_IPCD … #define SHIM_ISRSC … #define SHIM_ISRLPESC … #define SHIM_IMRSC … #define SHIM_IMRLPESC … #define SHIM_IPCSC … #define SHIM_IPCLPESC … #define SHIM_CLKCTL … #define SHIM_CSR2 … #define SHIM_LTRC … #define SHIM_HMDC … #define SHIM_PWMCTRL … /* * SST SHIM register bits for BYT, BSW, CHT, BDW * Register bit naming and functionaility can differ between devices. */ /* CSR / CS */ #define SHIM_CSR_RST … #define SHIM_CSR_SBCS0 … #define SHIM_CSR_SBCS1 … #define SHIM_CSR_DCS(x) … #define SHIM_CSR_DCS_MASK … #define SHIM_CSR_STALL … #define SHIM_CSR_S0IOCS … #define SHIM_CSR_S1IOCS … #define SHIM_CSR_LPCS … #define SHIM_CSR_24MHZ_LPCS … #define SHIM_CSR_24MHZ_NO_LPCS … #define SHIM_BYT_CSR_RST … #define SHIM_BYT_CSR_VECTOR_SEL … #define SHIM_BYT_CSR_STALL … #define SHIM_BYT_CSR_PWAITMODE … /* ISRX / ISC */ #define SHIM_ISRX_BUSY … #define SHIM_ISRX_DONE … #define SHIM_BYT_ISRX_REQUEST … /* ISRD / ISD */ #define SHIM_ISRD_BUSY … #define SHIM_ISRD_DONE … /* IMRX / IMC */ #define SHIM_IMRX_BUSY … #define SHIM_IMRX_DONE … #define SHIM_BYT_IMRX_REQUEST … /* IMRD / IMD */ #define SHIM_IMRD_DONE … #define SHIM_IMRD_BUSY … #define SHIM_IMRD_SSP0 … #define SHIM_IMRD_DMAC0 … #define SHIM_IMRD_DMAC1 … #define SHIM_IMRD_DMAC … /* IPCX / IPCC */ #define SHIM_IPCX_DONE … #define SHIM_IPCX_BUSY … #define SHIM_BYT_IPCX_DONE … #define SHIM_BYT_IPCX_BUSY … /* IPCD */ #define SHIM_IPCD_DONE … #define SHIM_IPCD_BUSY … #define SHIM_BYT_IPCD_DONE … #define SHIM_BYT_IPCD_BUSY … /* CLKCTL */ #define SHIM_CLKCTL_SMOS(x) … #define SHIM_CLKCTL_MASK … #define SHIM_CLKCTL_DCPLCG … #define SHIM_CLKCTL_SCOE1 … #define SHIM_CLKCTL_SCOE0 … /* CSR2 / CS2 */ #define SHIM_CSR2_SDFD_SSP0 … #define SHIM_CSR2_SDFD_SSP1 … /* LTRC */ #define SHIM_LTRC_VAL(x) … /* HMDC */ #define SHIM_HMDC_HDDA0(x) … #define SHIM_HMDC_HDDA1(x) … #define SHIM_HMDC_HDDA_E0_CH0 … #define SHIM_HMDC_HDDA_E0_CH1 … #define SHIM_HMDC_HDDA_E0_CH2 … #define SHIM_HMDC_HDDA_E0_CH3 … #define SHIM_HMDC_HDDA_E1_CH0 … #define SHIM_HMDC_HDDA_E1_CH1 … #define SHIM_HMDC_HDDA_E1_CH2 … #define SHIM_HMDC_HDDA_E1_CH3 … #define SHIM_HMDC_HDDA_E0_ALLCH … #define SHIM_HMDC_HDDA_E1_ALLCH … /* Audio DSP PCI registers */ #define PCI_VDRTCTL0 … #define PCI_VDRTCTL1 … #define PCI_VDRTCTL2 … #define PCI_VDRTCTL3 … /* VDRTCTL0 */ #define PCI_VDRTCL0_D3PGD … #define PCI_VDRTCL0_D3SRAMPGD … #define PCI_VDRTCL0_DSRAMPGE_SHIFT … #define PCI_VDRTCL0_DSRAMPGE_MASK … #define PCI_VDRTCL0_ISRAMPGE_SHIFT … #define PCI_VDRTCL0_ISRAMPGE_MASK … /* VDRTCTL2 */ #define PCI_VDRTCL2_DCLCGE … #define PCI_VDRTCL2_DTCGE … #define PCI_VDRTCL2_APLLSE_MASK … /* PMCS */ #define PCI_PMCS … #define PCI_PMCS_PS_MASK … /* Intel quirks */ #define SOF_INTEL_PROCEN_FMT_QUIRK … /* DSP hardware descriptor */ struct sof_intel_dsp_desc { … }; extern const struct snd_sof_dsp_ops sof_tng_ops; extern const struct sof_intel_dsp_desc tng_chip_info; struct sof_intel_stream { … }; static inline const struct sof_intel_dsp_desc *get_chip_info(struct snd_sof_pdata *pdata) { … } #endif
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