/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * Copyright(c) 2017 Intel Corporation * * Author: Liam Girdwood <[email protected]> */ #ifndef __SOF_INTEL_HDA_H #define __SOF_INTEL_HDA_H #include <linux/completion.h> #include <linux/soundwire/sdw.h> #include <linux/soundwire/sdw_intel.h> #include <sound/compress_driver.h> #include <sound/hda_codec.h> #include <sound/hdaudio_ext.h> #include "../sof-client-probes.h" #include "../sof-audio.h" #include "shim.h" /* PCI registers */ #define PCI_TCSEL … #define PCI_PGCTL … #define PCI_CGCTL … /* PCI_PGCTL bits */ #define PCI_PGCTL_ADSPPGD … #define PCI_PGCTL_LSRMD_MASK … /* PCI_CGCTL bits */ #define PCI_CGCTL_MISCBDCGE_MASK … #define PCI_CGCTL_ADSPDCGE … /* Legacy HDA registers and bits used - widths are variable */ #define SOF_HDA_GCAP … #define SOF_HDA_GCTL … /* accept unsol. response enable */ #define SOF_HDA_GCTL_UNSOL … #define SOF_HDA_LLCH … #define SOF_HDA_INTCTL … #define SOF_HDA_INTSTS … #define SOF_HDA_WAKESTS … #define SOF_HDA_WAKESTS_INT_MASK … #define SOF_HDA_RIRBSTS … /* SOF_HDA_GCTL register bist */ #define SOF_HDA_GCTL_RESET … /* SOF_HDA_INCTL regs */ #define SOF_HDA_INT_GLOBAL_EN … #define SOF_HDA_INT_CTRL_EN … #define SOF_HDA_INT_ALL_STREAM … /* SOF_HDA_INTSTS regs */ #define SOF_HDA_INTSTS_GIS … #define SOF_HDA_MAX_CAPS … #define SOF_HDA_CAP_ID_OFF … #define SOF_HDA_CAP_ID_MASK … #define SOF_HDA_CAP_NEXT_MASK … #define SOF_HDA_GTS_CAP_ID … #define SOF_HDA_ML_CAP_ID … #define SOF_HDA_PP_CAP_ID … #define SOF_HDA_REG_PP_PPCH … #define SOF_HDA_REG_PP_PPCTL … #define SOF_HDA_REG_PP_PPSTS … #define SOF_HDA_PPCTL_PIE … #define SOF_HDA_PPCTL_GPROCEN … /*Vendor Specific Registers*/ #define SOF_HDA_VS_D0I3C … /* D0I3C Register fields */ #define SOF_HDA_VS_D0I3C_CIP … #define SOF_HDA_VS_D0I3C_I3 … /* DPIB entry size: 8 Bytes = 2 DWords */ #define SOF_HDA_DPIB_ENTRY_SIZE … #define SOF_HDA_SPIB_CAP_ID … #define SOF_HDA_DRSM_CAP_ID … #define SOF_HDA_SPIB_BASE … #define SOF_HDA_SPIB_INTERVAL … #define SOF_HDA_SPIB_SPIB … #define SOF_HDA_SPIB_MAXFIFO … #define SOF_HDA_PPHC_BASE … #define SOF_HDA_PPHC_INTERVAL … #define SOF_HDA_PPLC_BASE … #define SOF_HDA_PPLC_MULTI … #define SOF_HDA_PPLC_INTERVAL … #define SOF_HDA_DRSM_BASE … #define SOF_HDA_DRSM_INTERVAL … /* Descriptor error interrupt */ #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR … /* FIFO error interrupt */ #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR … /* Buffer completion interrupt */ #define SOF_HDA_CL_DMA_SD_INT_COMPLETE … #define SOF_HDA_CL_DMA_SD_INT_MASK … #define SOF_HDA_SD_CTL_DMA_START … /* Intel HD Audio Code Loader DMA Registers */ #define SOF_HDA_ADSP_LOADER_BASE … #define SOF_HDA_ADSP_DPLBASE … #define SOF_HDA_ADSP_DPUBASE … #define SOF_HDA_ADSP_DPLBASE_ENABLE … /* Stream Registers */ #define SOF_HDA_ADSP_REG_SD_CTL … #define SOF_HDA_ADSP_REG_SD_STS … #define SOF_HDA_ADSP_REG_SD_LPIB … #define SOF_HDA_ADSP_REG_SD_CBL … #define SOF_HDA_ADSP_REG_SD_LVI … #define SOF_HDA_ADSP_REG_SD_FIFOW … #define SOF_HDA_ADSP_REG_SD_FIFOSIZE … #define SOF_HDA_ADSP_REG_SD_FORMAT … #define SOF_HDA_ADSP_REG_SD_FIFOL … #define SOF_HDA_ADSP_REG_SD_BDLPL … #define SOF_HDA_ADSP_REG_SD_BDLPU … #define SOF_HDA_ADSP_SD_ENTRY_SIZE … /* SDxFIFOS FIFOS */ #define SOF_HDA_SD_FIFOSIZE_FIFOS_MASK … /* CL: Software Position Based FIFO Capability Registers */ #define SOF_DSP_REG_CL_SPBFIFO … #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH … #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL … #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB … #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS … /* Stream Number */ #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT … #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK … #define HDA_DSP_HDA_BAR … #define HDA_DSP_PP_BAR … #define HDA_DSP_SPIB_BAR … #define HDA_DSP_DRSM_BAR … #define HDA_DSP_BAR … #define SRAM_WINDOW_OFFSET(x) … #define HDA_DSP_MBOX_OFFSET … #define HDA_DSP_PANIC_OFFSET(x) … /* SRAM window 0 FW "registers" */ #define HDA_DSP_SRAM_REG_ROM_STATUS … #define HDA_DSP_SRAM_REG_ROM_ERROR … /* FW and ROM share offset 4 */ #define HDA_DSP_SRAM_REG_FW_STATUS … #define HDA_DSP_SRAM_REG_FW_TRACEP … #define HDA_DSP_SRAM_REG_FW_END … #define HDA_DSP_MBOX_UPLINK_OFFSET … #define HDA_DSP_STREAM_RESET_TIMEOUT … /* * Timeout in us, for setting the stream RUN bit, during * start/stop the stream. The timeout expires if new RUN bit * value cannot be read back within the specified time. */ #define HDA_DSP_STREAM_RUN_TIMEOUT … #define HDA_DSP_SPIB_ENABLE … #define HDA_DSP_SPIB_DISABLE … #define SOF_HDA_MAX_BUFFER_SIZE … #define HDA_DSP_STACK_DUMP_SIZE … /* ROM/FW status register */ #define FSR_STATE_MASK … #define FSR_WAIT_STATE_MASK … #define FSR_MODULE_MASK … #define FSR_HALTED … #define FSR_TO_STATE_CODE(x) … #define FSR_TO_WAIT_STATE_CODE(x) … #define FSR_TO_MODULE_CODE(x) … /* Wait states */ #define FSR_WAIT_FOR_IPC_BUSY … #define FSR_WAIT_FOR_IPC_DONE … #define FSR_WAIT_FOR_CACHE_INVALIDATION … #define FSR_WAIT_FOR_LP_SRAM_OFF … #define FSR_WAIT_FOR_DMA_BUFFER_FULL … #define FSR_WAIT_FOR_CSE_CSR … /* Module codes */ #define FSR_MOD_ROM … #define FSR_MOD_ROM_BYP … #define FSR_MOD_BASE_FW … #define FSR_MOD_LP_BOOT … #define FSR_MOD_BRNGUP … #define FSR_MOD_ROM_EXT … /* State codes (module dependent) */ /* Module independent states */ #define FSR_STATE_INIT … #define FSR_STATE_INIT_DONE … #define FSR_STATE_FW_ENTERED … /* ROM states */ #define FSR_STATE_ROM_INIT … #define FSR_STATE_ROM_INIT_DONE … #define FSR_STATE_ROM_CSE_MANIFEST_LOADED … #define FSR_STATE_ROM_FW_MANIFEST_LOADED … #define FSR_STATE_ROM_FW_FW_LOADED … #define FSR_STATE_ROM_FW_ENTERED … #define FSR_STATE_ROM_VERIFY_FEATURE_MASK … #define FSR_STATE_ROM_GET_LOAD_OFFSET … #define FSR_STATE_ROM_FETCH_ROM_EXT … #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE … #define FSR_STATE_ROM_BASEFW_ENTERED … /* (ROM) CSE states */ #define FSR_STATE_ROM_CSE_IMR_REQUEST … #define FSR_STATE_ROM_CSE_IMR_GRANTED … #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST … #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED … #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT … #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 … #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY … #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL … #define FSR_STATE_ROM_CSE_IPC_DOWN … /* BRINGUP (or BRNGUP) states */ #define FSR_STATE_BRINGUP_INIT … #define FSR_STATE_BRINGUP_INIT_DONE … #define FSR_STATE_BRINGUP_HPSRAM_LOAD … #define FSR_STATE_BRINGUP_UNPACK_START … #define FSR_STATE_BRINGUP_IMR_RESTORE … #define FSR_STATE_BRINGUP_FW_ENTERED … /* ROM status/error values */ #define HDA_DSP_ROM_CSE_ERROR … #define HDA_DSP_ROM_CSE_WRONG_RESPONSE … #define HDA_DSP_ROM_IMR_TO_SMALL … #define HDA_DSP_ROM_BASE_FW_NOT_FOUND … #define HDA_DSP_ROM_CSE_VALIDATION_FAILED … #define HDA_DSP_ROM_IPC_FATAL_ERROR … #define HDA_DSP_ROM_L2_CACHE_ERROR … #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL … #define HDA_DSP_ROM_API_PTR_INVALID … #define HDA_DSP_ROM_BASEFW_INCOMPAT … #define HDA_DSP_ROM_UNHANDLED_INTERRUPT … #define HDA_DSP_ROM_MEMORY_HOLE_ECC … #define HDA_DSP_ROM_KERNEL_EXCEPTION … #define HDA_DSP_ROM_USER_EXCEPTION … #define HDA_DSP_ROM_UNEXPECTED_RESET … #define HDA_DSP_ROM_NULL_FW_ENTRY … #define HDA_DSP_ROM_IPC_CONTROL … #define HDA_DSP_ROM_IPC_PURGE_FW … /* various timeout values */ #define HDA_DSP_PU_TIMEOUT … #define HDA_DSP_PD_TIMEOUT … #define HDA_DSP_RESET_TIMEOUT_US … #define HDA_DSP_BASEFW_TIMEOUT_US … #define HDA_DSP_INIT_TIMEOUT_US … #define HDA_DSP_CTRL_RESET_TIMEOUT … #define HDA_DSP_WAIT_TIMEOUT … #define HDA_DSP_REG_POLL_INTERVAL_US … #define HDA_DSP_REG_POLL_RETRY_COUNT … #define HDA_DSP_ADSPIC_IPC … #define HDA_DSP_ADSPIS_IPC … /* Intel HD Audio General DSP Registers */ #define HDA_DSP_GEN_BASE … #define HDA_DSP_REG_ADSPCS … #define HDA_DSP_REG_ADSPIC … #define HDA_DSP_REG_ADSPIS … #define HDA_DSP_REG_ADSPIC2 … #define HDA_DSP_REG_ADSPIS2 … #define HDA_DSP_REG_ADSPIC2_SNDW … #define HDA_DSP_REG_ADSPIS2_SNDW … /* Intel HD Audio Inter-Processor Communication Registers */ #define HDA_DSP_IPC_BASE … #define HDA_DSP_REG_HIPCT … #define HDA_DSP_REG_HIPCTE … #define HDA_DSP_REG_HIPCI … #define HDA_DSP_REG_HIPCIE … #define HDA_DSP_REG_HIPCCTL … /* Intel Vendor Specific Registers */ #define HDA_VS_INTEL_EM2 … #define HDA_VS_INTEL_EM2_L1SEN … #define HDA_VS_INTEL_LTRP … #define HDA_VS_INTEL_LTRP_GB_MASK … /* HIPCI */ #define HDA_DSP_REG_HIPCI_BUSY … #define HDA_DSP_REG_HIPCI_MSG_MASK … /* HIPCIE */ #define HDA_DSP_REG_HIPCIE_DONE … #define HDA_DSP_REG_HIPCIE_MSG_MASK … /* HIPCCTL */ #define HDA_DSP_REG_HIPCCTL_DONE … #define HDA_DSP_REG_HIPCCTL_BUSY … /* HIPCT */ #define HDA_DSP_REG_HIPCT_BUSY … #define HDA_DSP_REG_HIPCT_MSG_MASK … /* HIPCTE */ #define HDA_DSP_REG_HIPCTE_MSG_MASK … #define HDA_DSP_ADSPIC_CL_DMA … #define HDA_DSP_ADSPIS_CL_DMA … /* Delay before scheduling D0i3 entry */ #define BXT_D0I3_DELAY … #define FW_CL_STREAM_NUMBER … #define HDA_FW_BOOT_ATTEMPTS … /* ADSPCS - Audio DSP Control & Status */ /* * Core Reset - asserted high * CRST Mask for a given core mask pattern, cm */ #define HDA_DSP_ADSPCS_CRST_SHIFT … #define HDA_DSP_ADSPCS_CRST_MASK(cm) … /* * Core run/stall - when set to '1' core is stalled * CSTALL Mask for a given core mask pattern, cm */ #define HDA_DSP_ADSPCS_CSTALL_SHIFT … #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) … /* * Set Power Active - when set to '1' turn cores on * SPA Mask for a given core mask pattern, cm */ #define HDA_DSP_ADSPCS_SPA_SHIFT … #define HDA_DSP_ADSPCS_SPA_MASK(cm) … /* * Current Power Active - power status of cores, set by hardware * CPA Mask for a given core mask pattern, cm */ #define HDA_DSP_ADSPCS_CPA_SHIFT … #define HDA_DSP_ADSPCS_CPA_MASK(cm) … /* * Mask for a given number of cores * nc = number of supported cores */ #define SOF_DSP_CORES_MASK(nc) … /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ #define CNL_DSP_IPC_BASE … #define CNL_DSP_REG_HIPCTDR … #define CNL_DSP_REG_HIPCTDA … #define CNL_DSP_REG_HIPCTDD … #define CNL_DSP_REG_HIPCIDR … #define CNL_DSP_REG_HIPCIDA … #define CNL_DSP_REG_HIPCIDD … #define CNL_DSP_REG_HIPCCTL … /* HIPCI */ #define CNL_DSP_REG_HIPCIDR_BUSY … #define CNL_DSP_REG_HIPCIDR_MSG_MASK … /* HIPCIE */ #define CNL_DSP_REG_HIPCIDA_DONE … #define CNL_DSP_REG_HIPCIDA_MSG_MASK … /* HIPCCTL */ #define CNL_DSP_REG_HIPCCTL_DONE … #define CNL_DSP_REG_HIPCCTL_BUSY … /* HIPCT */ #define CNL_DSP_REG_HIPCTDR_BUSY … #define CNL_DSP_REG_HIPCTDR_MSG_MASK … /* HIPCTDA */ #define CNL_DSP_REG_HIPCTDA_DONE … #define CNL_DSP_REG_HIPCTDA_MSG_MASK … /* HIPCTDD */ #define CNL_DSP_REG_HIPCTDD_MSG_MASK … /* BDL */ #define HDA_DSP_BDL_SIZE … #define HDA_DSP_MAX_BDL_ENTRIES … /* Number of DAIs */ #define SOF_SKL_NUM_DAIS_NOCODEC … #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) #define SOF_SKL_NUM_DAIS … #else #define SOF_SKL_NUM_DAIS … #endif /* Intel HD Audio SRAM Window 0*/ #define HDA_DSP_SRAM_REG_ROM_STATUS_SKL … #define HDA_ADSP_SRAM0_BASE_SKL … /* Firmware status window */ #define HDA_ADSP_FW_STATUS_SKL … #define HDA_ADSP_ERROR_CODE_SKL … /* Host Device Memory Space */ #define APL_SSP_BASE_OFFSET … #define CNL_SSP_BASE_OFFSET … /* Host Device Memory Size of a Single SSP */ #define SSP_DEV_MEM_SIZE … /* SSP Count of the Platform */ #define APL_SSP_COUNT … #define CNL_SSP_COUNT … #define ICL_SSP_COUNT … #define TGL_SSP_COUNT … #define MTL_SSP_COUNT … /* SSP Registers */ #define SSP_SSC1_OFFSET … #define SSP_SET_SCLK_CONSUMER … #define SSP_SET_SFRM_CONSUMER … #define SSP_SET_CBP_CFP … #define HDA_EXT_ADDR … #define HDA_EXT_CODEC(x) … #define HDA_IDISP_ADDR … #define HDA_IDISP_CODEC(x) … struct sof_intel_dsp_bdl { … } __attribute((packed)); #define SOF_HDA_PLAYBACK_STREAMS … #define SOF_HDA_CAPTURE_STREAMS … #define SOF_HDA_PLAYBACK … #define SOF_HDA_CAPTURE … /* stream flags */ #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE … /* * Time in ms for opportunistic D0I3 entry delay. * This has been deliberately chosen to be long to avoid race conditions. * Could be optimized in future. */ #define SOF_HDA_D0I3_WORK_DELAY_MS … /* HDA DSP D0 substate */ enum sof_hda_D0_substate { … }; /* represents DSP HDA controller frontend - i.e. host facing control */ struct sof_intel_hda_dev { … }; static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) { … } static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) { … } struct sof_intel_hda_stream { … }; #define hstream_to_sof_hda_stream(hstream) … #define bus_to_sof_hda(bus) … #define SOF_STREAM_SD_OFFSET(s) … #define SOF_STREAM_SD_OFFSET_CRST … /* * DAI support */ bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type); /* * DSP Core services. */ int hda_dsp_probe_early(struct snd_sof_dev *sdev); int hda_dsp_probe(struct snd_sof_dev *sdev); void hda_dsp_remove(struct snd_sof_dev *sdev); void hda_dsp_remove_late(struct snd_sof_dev *sdev); int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, unsigned int core_mask); int hda_power_down_dsp(struct snd_sof_dev *sdev); int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask); int hda_dsp_set_power_state_ipc3(struct snd_sof_dev *sdev, const struct sof_dsp_power_state *target_state); int hda_dsp_set_power_state_ipc4(struct snd_sof_dev *sdev, const struct sof_dsp_power_state *target_state); int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); int hda_dsp_resume(struct snd_sof_dev *sdev); int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev); int hda_dsp_shutdown(struct snd_sof_dev *sdev); int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags); void hda_ipc_dump(struct snd_sof_dev *sdev); void hda_ipc_irq_dump(struct snd_sof_dev *sdev); void hda_dsp_d0i3_work(struct work_struct *work); int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev); bool hda_check_ipc_irq(struct snd_sof_dev *sdev); u32 hda_get_interface_mask(struct snd_sof_dev *sdev); /* * DSP PCM Operations. */ u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); int hda_dsp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); int hda_dsp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_sof_platform_stream_params *platform_params); int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, int cmd); snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); /* * DSP Stream Operations. */ int hda_dsp_stream_init(struct snd_sof_dev *sdev); void hda_dsp_stream_free(struct snd_sof_dev *sdev); int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, struct snd_dma_buffer *dmab, struct snd_pcm_hw_params *params); int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, struct snd_dma_buffer *dmab, struct snd_pcm_hw_params *params); int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, int cmd); irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, struct hdac_stream *hstream); bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, int direction, bool can_sleep); u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev, struct snd_soc_component *component, struct snd_pcm_substream *substream); u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev, struct snd_soc_component *component, struct snd_pcm_substream *substream); struct hdac_ext_stream * hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream, int enable, u32 size); int hda_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, void *p, size_t sz); int hda_set_stream_data_offset(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, size_t posn_offset); /* * DSP IPC Operations. */ int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level); void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, u32 flags); /* * DSP Code loader. */ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream); struct hdac_ext_stream *hda_cl_prepare(struct device *dev, unsigned int format, unsigned int size, struct snd_dma_buffer *dmab, int direction, bool is_iccmax); int hda_cl_trigger(struct device *dev, struct hdac_ext_stream *hext_stream, int cmd); int hda_cl_cleanup(struct device *dev, struct snd_dma_buffer *dmab, struct hdac_ext_stream *hext_stream); int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); #define HDA_CL_STREAM_FORMAT … /* pre and post fw run ops */ int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); /* parse platform specific ext manifest ops */ int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, const struct sof_ext_man_elem_header *hdr); /* * HDA Controller Operations. */ int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev); void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); /* * HDA bus operations. */ void sof_hda_bus_init(struct snd_sof_dev *sdev, struct device *dev); void sof_hda_bus_exit(struct snd_sof_dev *sdev); #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) /* * HDA Codec operations. */ void hda_codec_probe_bus(struct snd_sof_dev *sdev); void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); void hda_codec_jack_check(struct snd_sof_dev *sdev); void hda_codec_check_for_state_change(struct snd_sof_dev *sdev); void hda_codec_init_cmd_io(struct snd_sof_dev *sdev); void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev); void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev); void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev); void hda_codec_detect_mask(struct snd_sof_dev *sdev); void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev); bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev); void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status); void hda_codec_device_remove(struct snd_sof_dev *sdev); #else static inline void hda_codec_probe_bus(struct snd_sof_dev *sdev) { } static inline void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable) { } static inline void hda_codec_jack_check(struct snd_sof_dev *sdev) { } static inline void hda_codec_check_for_state_change(struct snd_sof_dev *sdev) { } static inline void hda_codec_init_cmd_io(struct snd_sof_dev *sdev) { } static inline void hda_codec_resume_cmd_io(struct snd_sof_dev *sdev) { } static inline void hda_codec_stop_cmd_io(struct snd_sof_dev *sdev) { } static inline void hda_codec_suspend_cmd_io(struct snd_sof_dev *sdev) { } static inline void hda_codec_detect_mask(struct snd_sof_dev *sdev) { } static inline void hda_codec_rirb_status_clear(struct snd_sof_dev *sdev) { } static inline bool hda_codec_check_rirb_status(struct snd_sof_dev *sdev) { return false; } static inline void hda_codec_set_codec_wakeup(struct snd_sof_dev *sdev, bool status) { } static inline void hda_codec_device_remove(struct snd_sof_dev *sdev) { } #endif /* CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC */ #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) && IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); int hda_codec_i915_init(struct snd_sof_dev *sdev); int hda_codec_i915_exit(struct snd_sof_dev *sdev); #else static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable) { } static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } #endif /* * Trace Control. */ int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, struct sof_ipc_dma_trace_params_ext *dtrace_params); int hda_dsp_trace_release(struct snd_sof_dev *sdev); int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); /* * SoundWire support */ #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev); int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev); int hda_sdw_check_lcount(struct snd_sof_dev *sdev); int hda_sdw_startup(struct snd_sof_dev *sdev); void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable); void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev); void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev); void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); #else static inline int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) { return 0; } static inline int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) { return 0; } static inline int hda_sdw_check_lcount(struct snd_sof_dev *sdev) { return 0; } static inline int hda_sdw_startup(struct snd_sof_dev *sdev) { return 0; } static inline void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) { } static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) { } static inline bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev) { return false; } static inline void hda_sdw_process_wakeen_common(struct snd_sof_dev *sdev) { } static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) { } static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) { return false; } #endif int sdw_hda_dai_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *cpu_dai, int link_id, int intel_alh_id); int sdw_hda_dai_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai, int link_id); int sdw_hda_dai_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *cpu_dai); /* common dai driver */ extern struct snd_soc_dai_driver skl_dai[]; int hda_dsp_dais_suspend(struct snd_sof_dev *sdev); /* * Platform Specific HW abstraction Ops. */ extern const struct snd_sof_dsp_ops sof_hda_common_ops; extern struct snd_sof_dsp_ops sof_skl_ops; int sof_skl_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_apl_ops; int sof_apl_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_cnl_ops; int sof_cnl_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_tgl_ops; int sof_tgl_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_icl_ops; int sof_icl_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_mtl_ops; int sof_mtl_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_lnl_ops; int sof_lnl_ops_init(struct snd_sof_dev *sdev); extern const struct sof_intel_dsp_desc skl_chip_info; extern const struct sof_intel_dsp_desc apl_chip_info; extern const struct sof_intel_dsp_desc cnl_chip_info; extern const struct sof_intel_dsp_desc icl_chip_info; extern const struct sof_intel_dsp_desc tgl_chip_info; extern const struct sof_intel_dsp_desc tglh_chip_info; extern const struct sof_intel_dsp_desc ehl_chip_info; extern const struct sof_intel_dsp_desc jsl_chip_info; extern const struct sof_intel_dsp_desc adls_chip_info; extern const struct sof_intel_dsp_desc mtl_chip_info; extern const struct sof_intel_dsp_desc arl_s_chip_info; extern const struct sof_intel_dsp_desc lnl_chip_info; extern const struct sof_intel_dsp_desc ptl_chip_info; /* Probes support */ #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) int hda_probes_register(struct snd_sof_dev *sdev); void hda_probes_unregister(struct snd_sof_dev *sdev); #else static inline int hda_probes_register(struct snd_sof_dev *sdev) { return 0; } static inline void hda_probes_unregister(struct snd_sof_dev *sdev) { } #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ /* SOF client registration for HDA platforms */ int hda_register_clients(struct snd_sof_dev *sdev); void hda_unregister_clients(struct snd_sof_dev *sdev); /* machine driver select */ struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); void hda_set_mach_params(struct snd_soc_acpi_mach *mach, struct snd_sof_dev *sdev); /* PCI driver selection and probe */ int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); struct snd_sof_dai; struct sof_ipc_dai_config; #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY … #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS … #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE … extern int sof_hda_position_quirk; void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); void hda_ops_free(struct snd_sof_dev *sdev); /* SKL/KBL */ int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev); int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask); /* IPC4 */ irqreturn_t cnl_ipc4_irq_thread(int irq, void *context); int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context); bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev); void hda_dsp_ipc4_schedule_d0i3_work(struct sof_intel_hda_dev *hdev, struct snd_sof_ipc_msg *msg); int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); void hda_ipc4_dump(struct snd_sof_dev *sdev); extern struct sdw_intel_ops sdw_callback; struct sof_ipc4_fw_library; int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev, struct sof_ipc4_fw_library *fw_lib, bool reload); /** * struct hda_dai_widget_dma_ops - DAI DMA ops optional by default unless specified otherwise * @get_hext_stream: Mandatory function pointer to get the saved pointer to struct hdac_ext_stream * @assign_hext_stream: Function pointer to assign a hdac_ext_stream * @release_hext_stream: Function pointer to release the hdac_ext_stream * @setup_hext_stream: Function pointer for hdac_ext_stream setup * @reset_hext_stream: Function pointer for hdac_ext_stream reset * @pre_trigger: Function pointer for DAI DMA pre-trigger actions * @trigger: Function pointer for DAI DMA trigger actions * @post_trigger: Function pointer for DAI DMA post-trigger actions * @codec_dai_set_stream: Function pointer to set codec-side stream information * @calc_stream_format: Function pointer to determine stream format from hw_params and * for HDaudio codec DAI from the .sig bits * @get_hlink: Mandatory function pointer to retrieve hlink, mainly to program LOSIDV * for legacy HDaudio links or program HDaudio Extended Link registers. */ struct hda_dai_widget_dma_ops { … }; const struct hda_dai_widget_dma_ops * hda_select_dai_widget_ops(struct snd_sof_dev *sdev, struct snd_sof_widget *swidget); int hda_dai_config(struct snd_soc_dapm_widget *w, unsigned int flags, struct snd_sof_dai_config_data *data); int hda_link_dma_cleanup(struct snd_pcm_substream *substream, struct hdac_ext_stream *hext_stream, struct snd_soc_dai *cpu_dai); static inline struct snd_sof_dev *widget_to_sdev(struct snd_soc_dapm_widget *w) { … } #endif
Codebase Browser
linux