linux/sound/soc/sof/intel/hda-loader-skl.c

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license.  When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018-2022 Intel Corporation
//

#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <sound/hdaudio_ext.h>
#include <sound/sof.h>
#include <sound/pcm_params.h>

#include "../sof-priv.h"
#include "../ops.h"
#include "hda.h"

#define HDA_SKL_WAIT_TIMEOUT …
#define HDA_SKL_CLDMA_MAX_BUFFER_SIZE …

/* Stream Reset */
#define HDA_CL_SD_CTL_SRST_SHIFT …
#define HDA_CL_SD_CTL_SRST(x) …

/* Stream Run */
#define HDA_CL_SD_CTL_RUN_SHIFT …
#define HDA_CL_SD_CTL_RUN(x) …

/* Interrupt On Completion Enable */
#define HDA_CL_SD_CTL_IOCE_SHIFT …
#define HDA_CL_SD_CTL_IOCE(x) …

/* FIFO Error Interrupt Enable */
#define HDA_CL_SD_CTL_FEIE_SHIFT …
#define HDA_CL_SD_CTL_FEIE(x) …

/* Descriptor Error Interrupt Enable */
#define HDA_CL_SD_CTL_DEIE_SHIFT …
#define HDA_CL_SD_CTL_DEIE(x) …

/* FIFO Limit Change */
#define HDA_CL_SD_CTL_FIFOLC_SHIFT …
#define HDA_CL_SD_CTL_FIFOLC(x) …

/* Stripe Control */
#define HDA_CL_SD_CTL_STRIPE_SHIFT …
#define HDA_CL_SD_CTL_STRIPE(x) …

/* Traffic Priority */
#define HDA_CL_SD_CTL_TP_SHIFT …
#define HDA_CL_SD_CTL_TP(x) …

/* Bidirectional Direction Control */
#define HDA_CL_SD_CTL_DIR_SHIFT …
#define HDA_CL_SD_CTL_DIR(x) …

/* Stream Number */
#define HDA_CL_SD_CTL_STRM_SHIFT …
#define HDA_CL_SD_CTL_STRM(x) …

#define HDA_CL_SD_CTL_INT(x) …

#define HDA_CL_SD_CTL_INT_MASK …

#define DMA_ADDRESS_128_BITS_ALIGNMENT …
#define BDL_ALIGN(x) …

/* Buffer Descriptor List Lower Base Address */
#define HDA_CL_SD_BDLPLBA_SHIFT …
#define HDA_CL_SD_BDLPLBA_MASK …
#define HDA_CL_SD_BDLPLBA(x) …

/* Buffer Descriptor List Upper Base Address */
#define HDA_CL_SD_BDLPUBA(x) …

/* Software Position in Buffer Enable */
#define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_SHIFT …
#define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE_MASK …

#define HDA_CL_SPBFIFO_SPBFCCTL_SPIBE(x) …

#define HDA_CL_DMA_SD_INT_COMPLETE …

static int cl_skl_cldma_setup_bdle(struct snd_sof_dev *sdev,
				   struct snd_dma_buffer *dmab_data,
				   __le32 **bdlp, int size, int with_ioc)
{ … }

static void cl_skl_cldma_stream_run(struct snd_sof_dev *sdev, bool enable)
{ … }

static void cl_skl_cldma_stream_clear(struct snd_sof_dev *sdev)
{ … }

static void cl_skl_cldma_setup_spb(struct snd_sof_dev *sdev,
				   unsigned int size, bool enable)
{ … }

static void cl_skl_cldma_set_intr(struct snd_sof_dev *sdev, bool enable)
{ … }

static void cl_skl_cldma_cleanup_spb(struct snd_sof_dev *sdev)
{ … }

static void cl_skl_cldma_setup_controller(struct snd_sof_dev *sdev,
					  struct snd_dma_buffer *dmab_bdl,
					  unsigned int max_size, u32 count)
{ … }

static int cl_stream_prepare_skl(struct snd_sof_dev *sdev,
				 struct snd_dma_buffer *dmab,
				 struct snd_dma_buffer *dmab_bdl)

{ … }

static void cl_cleanup_skl(struct snd_sof_dev *sdev,
			   struct snd_dma_buffer *dmab,
			   struct snd_dma_buffer *dmab_bdl)
{ … }

static int cl_dsp_init_skl(struct snd_sof_dev *sdev,
			   struct snd_dma_buffer *dmab,
			   struct snd_dma_buffer *dmab_bdl)
{ … }

static void cl_skl_cldma_fill_buffer(struct snd_sof_dev *sdev,
				     struct snd_dma_buffer *dmab,
				     unsigned int bufsize,
				     unsigned int copysize,
				     const void *curr_pos,
				     bool intr_enable)
{ … }

static int cl_skl_cldma_wait_interruptible(struct snd_sof_dev *sdev,
					   bool intr_wait)
{ … }

static int
cl_skl_cldma_copy_to_buf(struct snd_sof_dev *sdev,
			 struct snd_dma_buffer *dmab,
			 const void *bin,
			 u32 total_size, u32 bufsize)
{ … }

static int cl_copy_fw_skl(struct snd_sof_dev *sdev,
			  struct snd_dma_buffer *dmab)

{ … }

int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev)
{ … }