/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * Copyright(c) 2020-2022 Intel Corporation */ /* DSP Registers */ #define MTL_HFDSSCS … #define MTL_HFDSSCS_SPA_MASK … #define MTL_HFDSSCS_CPA_MASK … #define MTL_HFSNDWIE … #define MTL_HFPWRCTL … #define PTL_HFPWRCTL2 … #define MTL_HfPWRCTL_WPIOXPG(x) … #define MTL_HFPWRCTL_WPDSPHPXPG … #define MTL_HFPWRSTS … #define PTL_HFPWRSTS2 … #define MTL_HFPWRSTS_DSPHPXPGS_MASK … #define MTL_HFINTIPPTR … #define MTL_IRQ_INTEN_L_HOST_IPC_MASK … #define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK … #define MTL_HFINTIPPTR_PTR_MASK … #define MTL_HDA_VS_D0I3C … #define MTL_DSP2CXCAP_PRIMARY_CORE … #define MTL_DSP2CXCTL_PRIMARY_CORE … #define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK … #define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK … #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL … #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT … /* IPC Registers */ #define MTL_DSP_REG_HFIPCXTDR … #define MTL_DSP_REG_HFIPCXTDR_BUSY … #define MTL_DSP_REG_HFIPCXTDR_MSG_MASK … #define MTL_DSP_REG_HFIPCXTDA … #define MTL_DSP_REG_HFIPCXTDA_BUSY … #define MTL_DSP_REG_HFIPCXIDR … #define MTL_DSP_REG_HFIPCXIDR_BUSY … #define MTL_DSP_REG_HFIPCXIDR_MSG_MASK … #define MTL_DSP_REG_HFIPCXIDA … #define MTL_DSP_REG_HFIPCXIDA_DONE … #define MTL_DSP_REG_HFIPCXIDA_MSG_MASK … #define MTL_DSP_REG_HFIPCXCTL … #define MTL_DSP_REG_HFIPCXCTL_BUSY … #define MTL_DSP_REG_HFIPCXCTL_DONE … #define MTL_DSP_REG_HFIPCXTDDY … #define MTL_DSP_REG_HFIPCXIDDY … #define MTL_DSP_REG_HfHIPCIE … #define MTL_DSP_REG_HfHIPCIE_IE_MASK … #define MTL_DSP_REG_HfSNDWIE … #define MTL_DSP_REG_HfSNDWIE_IE_MASK … #define MTL_DSP_IRQSTS … #define MTL_DSP_IRQSTS_IPC … #define MTL_DSP_IRQSTS_SDW … #define MTL_DSP_REG_POLL_INTERVAL_US … /* Memory windows */ #define MTL_SRAM_WINDOW_OFFSET(x) … #define MTL_DSP_MBOX_UPLINK_OFFSET … #define MTL_DSP_MBOX_UPLINK_SIZE … #define MTL_DSP_MBOX_DOWNLINK_OFFSET … #define MTL_DSP_MBOX_DOWNLINK_SIZE … /* FW registers */ #define MTL_DSP_ROM_STS … #define MTL_DSP_ROM_ERROR … #define MTL_DSP_REG_HFFLGPXQWY … #define MTL_DSP_REG_HFFLGPXQWY_ERROR … /* FSR status codes */ #define FSR_STATE_ROM_RESET_VECTOR_DONE … #define FSR_STATE_ROM_PURGE_BOOT … #define FSR_STATE_ROM_RESTORE_BOOT … #define FSR_STATE_ROM_FW_ENTRY_POINT … #define FSR_STATE_ROM_VALIDATE_PUB_KEY … #define FSR_STATE_ROM_POWER_DOWN_HPSRAM … #define FSR_STATE_ROM_POWER_DOWN_ULPSRAM … #define FSR_STATE_ROM_POWER_UP_ULPSRAM_STACK … #define FSR_STATE_ROM_POWER_UP_HPSRAM_DMA … #define FSR_STATE_ROM_BEFORE_EP_POINTER_READ … #define FSR_STATE_ROM_VALIDATE_MANIFEST … #define FSR_STATE_ROM_VALIDATE_FW_MODULE … #define FSR_STATE_ROM_PROTECT_IMR_REGION … #define FSR_STATE_ROM_PUSH_MODEL_ROUTINE … #define FSR_STATE_ROM_PULL_MODEL_ROUTINE … #define FSR_STATE_ROM_VALIDATE_PKG_DIR … #define FSR_STATE_ROM_VALIDATE_CPD … #define FSR_STATE_ROM_VALIDATE_CSS_MAN_HEADER … #define FSR_STATE_ROM_VALIDATE_BLOB_SVN … #define FSR_STATE_ROM_VERIFY_IFWI_PARTITION … #define FSR_STATE_ROM_REMOVE_ACCESS_CONTROL … #define FSR_STATE_ROM_AUTH_BYPASS … #define FSR_STATE_ROM_AUTH_ENABLED … #define FSR_STATE_ROM_INIT_DMA … #define FSR_STATE_ROM_PURGE_FW_ENTRY … #define FSR_STATE_ROM_PURGE_FW_END … #define FSR_STATE_ROM_CLEAN_UP_BSS_DONE … #define FSR_STATE_ROM_IMR_RESTORE_ENTRY … #define FSR_STATE_ROM_IMR_RESTORE_END … #define FSR_STATE_ROM_FW_MANIFEST_IN_DMA_BUFF … #define FSR_STATE_ROM_LOAD_CSE_MAN_TO_IMR … #define FSR_STATE_ROM_LOAD_FW_MAN_TO_IMR … #define FSR_STATE_ROM_LOAD_FW_CODE_TO_IMR … #define FSR_STATE_ROM_FW_LOADING_DONE … #define FSR_STATE_ROM_FW_CODE_LOADED … #define FSR_STATE_ROM_VERIFY_IMAGE_TYPE … #define FSR_STATE_ROM_AUTH_API_INIT … #define FSR_STATE_ROM_AUTH_API_PROC … #define FSR_STATE_ROM_AUTH_API_FIRST_BUSY … #define FSR_STATE_ROM_AUTH_API_FIRST_RESULT … #define FSR_STATE_ROM_AUTH_API_CLEANUP … #define MTL_DSP_REG_HfIMRIS1 … #define MTL_DSP_REG_HfIMRIS1_IU_MASK … bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev); int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev); void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev); int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable); int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev); int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev); void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags); int mtl_power_down_dsp(struct snd_sof_dev *sdev); int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); irqreturn_t mtl_ipc_irq_thread(int irq, void *context); int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); void mtl_ipc_dump(struct snd_sof_dev *sdev); int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core); int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core);
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