linux/sound/soc/sof/intel/mtl.c

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright(c) 2022 Intel Corporation
//
// Authors: Ranjani Sridharan <[email protected]>
//

/*
 * Hardware interface for audio DSP on Meteorlake.
 */

#include <linux/debugfs.h>
#include <linux/firmware.h>
#include <sound/sof/ipc4/header.h>
#include <trace/events/sof_intel.h>
#include "../ipc4-priv.h"
#include "../ops.h"
#include "hda.h"
#include "hda-ipc.h"
#include "../sof-audio.h"
#include "mtl.h"
#include "telemetry.h"

static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] =;

static void mtl_ipc_host_done(struct snd_sof_dev *sdev)
{}

static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev)
{}

/* Check if an IPC IRQ occurred */
bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
{}
EXPORT_SYMBOL_NS();

/* Check if an SDW IRQ occurred */
static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
{}

int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
{}
EXPORT_SYMBOL_NS();

void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev)
{}

void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev)
{}
EXPORT_SYMBOL_NS();

static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
{}

int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable)
{}
EXPORT_SYMBOL_NS();

/* pre fw run operations */
int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
{}
EXPORT_SYMBOL_NS();

int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
{}
EXPORT_SYMBOL_NS();

void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{}
EXPORT_SYMBOL_NS();

static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev)
{}

static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core)
{}

static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core)
{}

int mtl_power_down_dsp(struct snd_sof_dev *sdev)
{}
EXPORT_SYMBOL_NS();

int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
{}
EXPORT_SYMBOL_NS();

irqreturn_t mtl_ipc_irq_thread(int irq, void *context)
{}
EXPORT_SYMBOL_NS();

int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
{}
EXPORT_SYMBOL_NS();

int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
{}
EXPORT_SYMBOL_NS();

void mtl_ipc_dump(struct snd_sof_dev *sdev)
{}
EXPORT_SYMBOL_NS();

static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
{}

int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core)
{}
EXPORT_SYMBOL_NS();

int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core)
{}
EXPORT_SYMBOL_NS();

/* Meteorlake ops */
struct snd_sof_dsp_ops sof_mtl_ops;

int sof_mtl_ops_init(struct snd_sof_dev *sdev)
{
	struct sof_ipc4_fw_data *ipc4_data;

	/* common defaults */
	memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));

	/* shutdown */
	sof_mtl_ops.shutdown = hda_dsp_shutdown;

	/* doorbell */
	sof_mtl_ops.irq_thread = mtl_ipc_irq_thread;

	/* ipc */
	sof_mtl_ops.send_msg = mtl_ipc_send_msg;
	sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
	sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;

	/* debug */
	sof_mtl_ops.debug_map = mtl_dsp_debugfs;
	sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs);
	sof_mtl_ops.dbg_dump = mtl_dsp_dump;
	sof_mtl_ops.ipc_dump = mtl_ipc_dump;

	/* pre/post fw run */
	sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
	sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run;

	/* parse platform specific extended manifest */
	sof_mtl_ops.parse_platform_ext_manifest = NULL;

	/* dsp core get/put */
	sof_mtl_ops.core_get = mtl_dsp_core_get;
	sof_mtl_ops.core_put = mtl_dsp_core_put;

	sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
	if (!sdev->private)
		return -ENOMEM;

	ipc4_data = sdev->private;
	ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;

	ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;

	ipc4_data->fw_context_save = true;

	/* External library loading support */
	ipc4_data->load_library = hda_dsp_ipc4_load_library;

	/* set DAI ops */
	hda_set_dai_drv_ops(sdev, &sof_mtl_ops);

	sof_mtl_ops.set_power_state = hda_dsp_set_power_state_ipc4;

	return 0;
};

const struct sof_intel_dsp_desc mtl_chip_info =;

const struct sof_intel_dsp_desc arl_s_chip_info =;