#ifndef _OMAP_DMIC_H
#define _OMAP_DMIC_H
#define OMAP_DMIC_REVISION_REG …
#define OMAP_DMIC_SYSCONFIG_REG …
#define OMAP_DMIC_IRQSTATUS_RAW_REG …
#define OMAP_DMIC_IRQSTATUS_REG …
#define OMAP_DMIC_IRQENABLE_SET_REG …
#define OMAP_DMIC_IRQENABLE_CLR_REG …
#define OMAP_DMIC_IRQWAKE_EN_REG …
#define OMAP_DMIC_DMAENABLE_SET_REG …
#define OMAP_DMIC_DMAENABLE_CLR_REG …
#define OMAP_DMIC_DMAWAKEEN_REG …
#define OMAP_DMIC_CTRL_REG …
#define OMAP_DMIC_DATA_REG …
#define OMAP_DMIC_FIFO_CTRL_REG …
#define OMAP_DMIC_FIFO_DMIC1R_DATA_REG …
#define OMAP_DMIC_FIFO_DMIC1L_DATA_REG …
#define OMAP_DMIC_FIFO_DMIC2R_DATA_REG …
#define OMAP_DMIC_FIFO_DMIC2L_DATA_REG …
#define OMAP_DMIC_FIFO_DMIC3R_DATA_REG …
#define OMAP_DMIC_FIFO_DMIC3L_DATA_REG …
#define OMAP_DMIC_IRQ …
#define OMAP_DMIC_IRQ_FULL …
#define OMAP_DMIC_IRQ_ALMST_EMPTY …
#define OMAP_DMIC_IRQ_EMPTY …
#define OMAP_DMIC_IRQ_MASK …
#define OMAP_DMIC_DMA_ENABLE …
#define OMAP_DMIC_UP1_ENABLE …
#define OMAP_DMIC_UP2_ENABLE …
#define OMAP_DMIC_UP3_ENABLE …
#define OMAP_DMIC_UP_ENABLE_MASK …
#define OMAP_DMIC_FORMAT …
#define OMAP_DMIC_POLAR1 …
#define OMAP_DMIC_POLAR2 …
#define OMAP_DMIC_POLAR3 …
#define OMAP_DMIC_POLAR_MASK …
#define OMAP_DMIC_CLK_DIV(x) …
#define OMAP_DMIC_CLK_DIV_MASK …
#define OMAP_DMIC_RESET …
#define OMAP_DMICOUTFORMAT_LJUST …
#define OMAP_DMICOUTFORMAT_RJUST …
#define OMAP_DMIC_THRES_MAX …
enum omap_dmic_clk { … };
#endif