// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Authors: Thomas Abraham <[email protected]> * Chander Kashyap <[email protected]> * * Common Clock Framework support for Exynos5420 SoC. */ #include <dt-bindings/clock/exynos5420.h> #include <linux/slab.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/clk.h> #include "clk.h" #include "clk-cpu.h" #include "clk-exynos5-subcmu.h" #define APLL_LOCK … #define APLL_CON0 … #define SRC_CPU … #define DIV_CPU0 … #define DIV_CPU1 … #define GATE_BUS_CPU … #define GATE_SCLK_CPU … #define CLKOUT_CMU_CPU … #define SRC_MASK_CPERI … #define GATE_IP_G2D … #define CPLL_LOCK … #define DPLL_LOCK … #define EPLL_LOCK … #define RPLL_LOCK … #define IPLL_LOCK … #define SPLL_LOCK … #define VPLL_LOCK … #define MPLL_LOCK … #define CPLL_CON0 … #define DPLL_CON0 … #define EPLL_CON0 … #define EPLL_CON1 … #define EPLL_CON2 … #define RPLL_CON0 … #define RPLL_CON1 … #define RPLL_CON2 … #define IPLL_CON0 … #define SPLL_CON0 … #define VPLL_CON0 … #define MPLL_CON0 … #define SRC_TOP0 … #define SRC_TOP1 … #define SRC_TOP2 … #define SRC_TOP3 … #define SRC_TOP4 … #define SRC_TOP5 … #define SRC_TOP6 … #define SRC_TOP7 … #define SRC_TOP8 … #define SRC_TOP9 … #define SRC_DISP10 … #define SRC_MAU … #define SRC_FSYS … #define SRC_PERIC0 … #define SRC_PERIC1 … #define SRC_ISP … #define SRC_CAM … #define SRC_TOP10 … #define SRC_TOP11 … #define SRC_TOP12 … #define SRC_TOP13 … #define SRC_MASK_TOP0 … #define SRC_MASK_TOP1 … #define SRC_MASK_TOP2 … #define SRC_MASK_TOP7 … #define SRC_MASK_DISP10 … #define SRC_MASK_MAU … #define SRC_MASK_FSYS … #define SRC_MASK_PERIC0 … #define SRC_MASK_PERIC1 … #define SRC_MASK_ISP … #define DIV_TOP0 … #define DIV_TOP1 … #define DIV_TOP2 … #define DIV_TOP8 … #define DIV_TOP9 … #define DIV_DISP10 … #define DIV_MAU … #define DIV_FSYS0 … #define DIV_FSYS1 … #define DIV_FSYS2 … #define DIV_PERIC0 … #define DIV_PERIC1 … #define DIV_PERIC2 … #define DIV_PERIC3 … #define DIV_PERIC4 … #define DIV_CAM … #define SCLK_DIV_ISP0 … #define SCLK_DIV_ISP1 … #define DIV2_RATIO0 … #define DIV4_RATIO … #define GATE_BUS_TOP … #define GATE_BUS_DISP1 … #define GATE_BUS_GEN … #define GATE_BUS_FSYS0 … #define GATE_BUS_FSYS2 … #define GATE_BUS_PERIC … #define GATE_BUS_PERIC1 … #define GATE_BUS_PERIS0 … #define GATE_BUS_PERIS1 … #define GATE_BUS_NOC … #define GATE_TOP_SCLK_ISP … #define GATE_IP_GSCL0 … #define GATE_IP_GSCL1 … #define GATE_IP_CAM … #define GATE_IP_MFC … #define GATE_IP_DISP1 … #define GATE_IP_G3D … #define GATE_IP_GEN … #define GATE_IP_FSYS … #define GATE_IP_PERIC … #define GATE_IP_PERIS … #define GATE_IP_MSCL … #define GATE_TOP_SCLK_GSCL … #define GATE_TOP_SCLK_DISP1 … #define GATE_TOP_SCLK_MAU … #define GATE_TOP_SCLK_FSYS … #define GATE_TOP_SCLK_PERIC … #define TOP_SPARE2 … #define BPLL_LOCK … #define BPLL_CON0 … #define SRC_CDREX … #define DIV_CDREX0 … #define DIV_CDREX1 … #define GATE_BUS_CDREX0 … #define GATE_BUS_CDREX1 … #define KPLL_LOCK … #define KPLL_CON0 … #define SRC_KFC … #define DIV_KFC0 … /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR … /* Exynos5x SoC type */ enum exynos5x_soc { … }; /* list of PLLs */ enum exynos5x_plls { … }; static void __iomem *reg_base; static enum exynos5x_soc exynos5x_soc; /* * list of controller registers to be saved and restored during a * suspend/resume cycle. */ static const unsigned long exynos5x_clk_regs[] __initconst = …; static const unsigned long exynos5800_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = …; /* list of all parent clocks */ PNAME(mout_mspll_cpu_p) = …; PNAME(mout_cpu_p) = …; PNAME(mout_kfc_p) = …; PNAME(mout_apll_p) = …; PNAME(mout_bpll_p) = …; PNAME(mout_cpll_p) = …; PNAME(mout_dpll_p) = …; PNAME(mout_epll_p) = …; PNAME(mout_ipll_p) = …; PNAME(mout_kpll_p) = …; PNAME(mout_mpll_p) = …; PNAME(mout_rpll_p) = …; PNAME(mout_spll_p) = …; PNAME(mout_vpll_p) = …; PNAME(mout_group1_p) = …; PNAME(mout_group2_p) = …; PNAME(mout_group3_p) = …; PNAME(mout_group4_p) = …; PNAME(mout_group5_p) = …; PNAME(mout_fimd1_final_p) = …; PNAME(mout_sw_aclk66_p) = …; PNAME(mout_user_aclk66_peric_p) = …; PNAME(mout_user_pclk66_gpio_p) = …; PNAME(mout_sw_aclk200_fsys_p) = …; PNAME(mout_sw_pclk200_fsys_p) = …; PNAME(mout_user_pclk200_fsys_p) = …; PNAME(mout_user_aclk200_fsys_p) = …; PNAME(mout_sw_aclk200_fsys2_p) = …; PNAME(mout_user_aclk200_fsys2_p) = …; PNAME(mout_sw_aclk100_noc_p) = …; PNAME(mout_user_aclk100_noc_p) = …; PNAME(mout_sw_aclk400_wcore_p) = …; PNAME(mout_aclk400_wcore_bpll_p) = …; PNAME(mout_user_aclk400_wcore_p) = …; PNAME(mout_sw_aclk400_isp_p) = …; PNAME(mout_user_aclk400_isp_p) = …; PNAME(mout_sw_aclk333_432_isp0_p) = …; PNAME(mout_user_aclk333_432_isp0_p) = …; PNAME(mout_sw_aclk333_432_isp_p) = …; PNAME(mout_user_aclk333_432_isp_p) = …; PNAME(mout_sw_aclk200_p) = …; PNAME(mout_user_aclk200_disp1_p) = …; PNAME(mout_sw_aclk400_mscl_p) = …; PNAME(mout_user_aclk400_mscl_p) = …; PNAME(mout_sw_aclk333_p) = …; PNAME(mout_user_aclk333_p) = …; PNAME(mout_sw_aclk166_p) = …; PNAME(mout_user_aclk166_p) = …; PNAME(mout_sw_aclk266_p) = …; PNAME(mout_user_aclk266_p) = …; PNAME(mout_user_aclk266_isp_p) = …; PNAME(mout_sw_aclk333_432_gscl_p) = …; PNAME(mout_user_aclk333_432_gscl_p) = …; PNAME(mout_sw_aclk300_gscl_p) = …; PNAME(mout_user_aclk300_gscl_p) = …; PNAME(mout_sw_aclk300_disp1_p) = …; PNAME(mout_sw_aclk400_disp1_p) = …; PNAME(mout_user_aclk300_disp1_p) = …; PNAME(mout_user_aclk400_disp1_p) = …; PNAME(mout_sw_aclk300_jpeg_p) = …; PNAME(mout_user_aclk300_jpeg_p) = …; PNAME(mout_sw_aclk_g3d_p) = …; PNAME(mout_user_aclk_g3d_p) = …; PNAME(mout_sw_aclk266_g2d_p) = …; PNAME(mout_user_aclk266_g2d_p) = …; PNAME(mout_sw_aclk333_g2d_p) = …; PNAME(mout_user_aclk333_g2d_p) = …; PNAME(mout_audio0_p) = …; PNAME(mout_audio1_p) = …; PNAME(mout_audio2_p) = …; PNAME(mout_spdif_p) = …; PNAME(mout_hdmi_p) = …; PNAME(mout_maudio0_p) = …; PNAME(mout_mau_epll_clk_p) = …; PNAME(mout_mclk_cdrex_p) = …; /* List of parents specific to exynos5800 */ PNAME(mout_epll2_5800_p) = …; PNAME(mout_group1_5800_p) = …; PNAME(mout_group2_5800_p) = …; PNAME(mout_group3_5800_p) = …; PNAME(mout_group5_5800_p) = …; PNAME(mout_group6_5800_p) = …; PNAME(mout_group7_5800_p) = …; PNAME(mout_mx_mspll_ccore_p) = …; PNAME(mout_mau_epll_clk_5800_p) = …; PNAME(mout_group8_5800_p) = …; PNAME(mout_group9_5800_p) = …; PNAME(mout_group10_5800_p) = …; PNAME(mout_group11_5800_p) = …; PNAME(mout_group12_5800_p) = …; PNAME(mout_group13_5800_p) = …; PNAME(mout_group14_5800_p) = …; PNAME(mout_group15_5800_p) = …; PNAME(mout_group16_5800_p) = …; PNAME(mout_mx_mspll_ccore_phy_p) = …; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5x_fixed_rate_ext_clks[] __initdata = …; /* fixed rate clocks generated inside the soc */ static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = …; static const struct samsung_fixed_factor_clock exynos5x_fixed_factor_clks[] __initconst = …; static const struct samsung_fixed_factor_clock exynos5800_fixed_factor_clks[] __initconst = …; static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = …; static const struct samsung_div_clock exynos5800_div_clks[] __initconst = …; static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = …; static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = …; static const struct samsung_div_clock exynos5420_div_clks[] __initconst = …; static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = …; static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = …; static const struct samsung_div_clock exynos5x_div_clks[] __initconst = …; static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = …; static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = …; static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = …; static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = …; static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = …; static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = …; static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = …; static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = …; static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = …; static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = …; static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = …; static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = …; static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = …; static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = …; static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = …; static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = …; static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = …; static const struct exynos5_subcmu_info exynos5x_disp_subcmu = …; static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = …; static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = …; static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = …; static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = …; static const struct exynos5_subcmu_info exynos5800_mau_subcmu = …; static const struct exynos5_subcmu_info *exynos5x_subcmus[] = …; static const struct exynos5_subcmu_info *exynos5800_subcmus[] = …; static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = …; static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = …; static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = …; static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = …; static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = …; #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) … static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = …; static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = …; #define E5420_KFC_DIV(kpll, pclk, aclk) … static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = …; static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = …; static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = …; static const struct of_device_id ext_clk_match[] __initconst = …; /* register exynos5420 clocks */ static void __init exynos5x_clk_init(struct device_node *np, enum exynos5x_soc soc) { … } static void __init exynos5420_clk_init(struct device_node *np) { … } CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); static void __init exynos5800_clk_init(struct device_node *np) { … } CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);
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