// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2021 Linaro Ltd. * Author: Sam Protsenko <[email protected]> * * Common Clock Framework support for Exynos850 SoC. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/exynos850.h> #include "clk.h" #include "clk-cpu.h" #include "clk-exynos-arm64.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP … #define CLKS_NR_APM … #define CLKS_NR_AUD … #define CLKS_NR_CMGP … #define CLKS_NR_CPUCL0 … #define CLKS_NR_CPUCL1 … #define CLKS_NR_G3D … #define CLKS_NR_HSI … #define CLKS_NR_IS … #define CLKS_NR_MFCMSCL … #define CLKS_NR_PERI … #define CLKS_NR_CORE … #define CLKS_NR_DPU … /* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x120e0000) */ #define PLL_LOCKTIME_PLL_MMC … #define PLL_LOCKTIME_PLL_SHARED0 … #define PLL_LOCKTIME_PLL_SHARED1 … #define PLL_CON0_PLL_MMC … #define PLL_CON3_PLL_MMC … #define PLL_CON0_PLL_SHARED0 … #define PLL_CON3_PLL_SHARED0 … #define PLL_CON0_PLL_SHARED1 … #define PLL_CON3_PLL_SHARED1 … #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS … #define CLK_CON_MUX_MUX_CLKCMU_AUD … #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS … #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI … #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD … #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_DPU … #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS … #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD … #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD … #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS … #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC … #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP … #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA … #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG … #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M … #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC … #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC … #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS … #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP … #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART … #define CLK_CON_DIV_CLKCMU_APM_BUS … #define CLK_CON_DIV_CLKCMU_AUD … #define CLK_CON_DIV_CLKCMU_CORE_BUS … #define CLK_CON_DIV_CLKCMU_CORE_CCI … #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD … #define CLK_CON_DIV_CLKCMU_CORE_SSS … #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG … #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_DIV_CLKCMU_CPUCL1_DBG … #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_DIV_CLKCMU_DPU … #define CLK_CON_DIV_CLKCMU_G3D_SWITCH … #define CLK_CON_DIV_CLKCMU_HSI_BUS … #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD … #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD … #define CLK_CON_DIV_CLKCMU_IS_BUS … #define CLK_CON_DIV_CLKCMU_IS_GDC … #define CLK_CON_DIV_CLKCMU_IS_ITP … #define CLK_CON_DIV_CLKCMU_IS_VRA … #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG … #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M … #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC … #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC … #define CLK_CON_DIV_CLKCMU_PERI_BUS … #define CLK_CON_DIV_CLKCMU_PERI_IP … #define CLK_CON_DIV_CLKCMU_PERI_UART … #define CLK_CON_DIV_PLL_SHARED0_DIV2 … #define CLK_CON_DIV_PLL_SHARED0_DIV3 … #define CLK_CON_DIV_PLL_SHARED0_DIV4 … #define CLK_CON_DIV_PLL_SHARED1_DIV2 … #define CLK_CON_DIV_PLL_SHARED1_DIV3 … #define CLK_CON_DIV_PLL_SHARED1_DIV4 … #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS … #define CLK_CON_GAT_GATE_CLKCMU_AUD … #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS … #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI … #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD … #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_DPU … #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS … #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD … #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD … #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS … #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC … #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP … #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA … #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG … #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M … #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC … #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC … #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS … #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP … #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART … static const unsigned long top_clk_regs[] __initconst = …; /* * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set * for those PLLs by default, so set_rate operation would fail. */ static const struct samsung_pll_clock top_pll_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_TOP */ PNAME(mout_shared0_pll_p) = …; PNAME(mout_shared1_pll_p) = …; PNAME(mout_mmc_pll_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */ PNAME(mout_clkcmu_apm_bus_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */ PNAME(mout_aud_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ PNAME(mout_core_bus_p) = …; PNAME(mout_core_cci_p) = …; PNAME(mout_core_mmc_embd_p) = …; PNAME(mout_core_sss_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */ PNAME(mout_cpucl0_switch_p) = …; PNAME(mout_cpucl0_dbg_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */ PNAME(mout_cpucl1_switch_p) = …; PNAME(mout_cpucl1_dbg_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ PNAME(mout_g3d_switch_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ PNAME(mout_hsi_bus_p) = …; PNAME(mout_hsi_mmc_card_p) = …; PNAME(mout_hsi_usb20drd_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */ PNAME(mout_is_bus_p) = …; PNAME(mout_is_itp_p) = …; PNAME(mout_is_vra_p) = …; PNAME(mout_is_gdc_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */ PNAME(mout_mfcmscl_mfc_p) = …; PNAME(mout_mfcmscl_m2m_p) = …; PNAME(mout_mfcmscl_mcsc_p) = …; PNAME(mout_mfcmscl_jpeg_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ PNAME(mout_peri_bus_p) = …; PNAME(mout_peri_uart_p) = …; PNAME(mout_peri_ip_p) = …; /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */ PNAME(mout_dpu_p) = …; static const struct samsung_mux_clock top_mux_clks[] __initconst = …; static const struct samsung_div_clock top_div_clks[] __initconst = …; static const struct samsung_gate_clock top_gate_clks[] __initconst = …; static const struct samsung_cmu_info top_cmu_info __initconst = …; static void __init exynos850_cmu_top_init(struct device_node *np) { … } /* Register CMU_TOP early, as it's a dependency for other early domains */ CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", exynos850_cmu_top_init); /* ---- CMU_APM ------------------------------------------------------------- */ /* Register Offset definitions for CMU_APM (0x11800000) */ #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER … #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER … #define PLL_CON0_MUX_CLK_RCO_APM_USER … #define PLL_CON0_MUX_DLL_USER … #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS … #define CLK_CON_MUX_MUX_CLK_APM_BUS … #define CLK_CON_MUX_MUX_CLK_APM_I3C … #define CLK_CON_DIV_CLKCMU_CHUB_BUS … #define CLK_CON_DIV_DIV_CLK_APM_BUS … #define CLK_CON_DIV_DIV_CLK_APM_I3C … #define CLK_CON_GAT_CLKCMU_CMGP_BUS … #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS … #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK … #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK … #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK … #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK … #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK … #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK … #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK … #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK … static const unsigned long apm_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_APM */ PNAME(mout_apm_bus_user_p) = …; PNAME(mout_rco_apm_i3c_user_p) = …; PNAME(mout_rco_apm_user_p) = …; PNAME(mout_dll_user_p) = …; PNAME(mout_clkcmu_chub_bus_p) = …; PNAME(mout_apm_bus_p) = …; PNAME(mout_apm_i3c_p) = …; static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = …; static const struct samsung_mux_clock apm_mux_clks[] __initconst = …; static const struct samsung_div_clock apm_div_clks[] __initconst = …; static const struct samsung_gate_clock apm_gate_clks[] __initconst = …; static const struct samsung_cmu_info apm_cmu_info __initconst = …; /* ---- CMU_AUD ------------------------------------------------------------- */ #define PLL_LOCKTIME_PLL_AUD … #define PLL_CON0_PLL_AUD … #define PLL_CON3_PLL_AUD … #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER … #define PLL_CON0_MUX_TICK_USB_USER … #define CLK_CON_MUX_MUX_CLK_AUD_CPU … #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH … #define CLK_CON_MUX_MUX_CLK_AUD_FM … #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 … #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 … #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 … #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 … #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 … #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 … #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 … #define CLK_CON_DIV_DIV_CLK_AUD_MCLK … #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF … #define CLK_CON_DIV_DIV_CLK_AUD_BUSD … #define CLK_CON_DIV_DIV_CLK_AUD_BUSP … #define CLK_CON_DIV_DIV_CLK_AUD_CNT … #define CLK_CON_DIV_DIV_CLK_AUD_CPU … #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK … #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG … #define CLK_CON_DIV_DIV_CLK_AUD_FM … #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY … #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 … #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 … #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 … #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 … #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 … #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 … #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 … #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK … #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK … #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY … #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB … #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 … #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP … #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK … #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK … #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK … #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK … #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK … #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 … #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK … #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK … static const unsigned long aud_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_AUD */ PNAME(mout_aud_pll_p) = …; PNAME(mout_aud_cpu_user_p) = …; PNAME(mout_aud_cpu_p) = …; PNAME(mout_aud_cpu_hch_p) = …; PNAME(mout_aud_uaif0_p) = …; PNAME(mout_aud_uaif1_p) = …; PNAME(mout_aud_uaif2_p) = …; PNAME(mout_aud_uaif3_p) = …; PNAME(mout_aud_uaif4_p) = …; PNAME(mout_aud_uaif5_p) = …; PNAME(mout_aud_uaif6_p) = …; PNAME(mout_aud_tick_usb_user_p) = …; PNAME(mout_aud_fm_p) = …; /* * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set * for that PLL by default, so set_rate operation would fail. */ static const struct samsung_pll_clock aud_pll_clks[] __initconst = …; static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = …; static const struct samsung_mux_clock aud_mux_clks[] __initconst = …; static const struct samsung_div_clock aud_div_clks[] __initconst = …; static const struct samsung_gate_clock aud_gate_clks[] __initconst = …; static const struct samsung_cmu_info aud_cmu_info __initconst = …; /* ---- CMU_CMGP ------------------------------------------------------------ */ /* Register Offset definitions for CMU_CMGP (0x11c00000) */ #define CLK_CON_MUX_CLK_CMGP_ADC … #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 … #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 … #define CLK_CON_DIV_DIV_CLK_CMGP_ADC … #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 … #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 … #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 … #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 … #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK … #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK … #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK … #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK … #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK … #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK … static const unsigned long cmgp_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_CMGP */ PNAME(mout_cmgp_usi0_p) = …; PNAME(mout_cmgp_usi1_p) = …; PNAME(mout_cmgp_adc_p) = …; static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = …; static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = …; static const struct samsung_div_clock cmgp_div_clks[] __initconst = …; static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = …; static const struct samsung_cmu_info cmgp_cmu_info __initconst = …; /* ---- CMU_CPUCL0 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_CPUCL0 (0x10900000) */ #define PLL_LOCKTIME_PLL_CPUCL0 … #define PLL_CON0_PLL_CPUCL0 … #define PLL_CON1_PLL_CPUCL0 … #define PLL_CON3_PLL_CPUCL0 … #define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER … #define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER … #define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL … #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK … #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK … #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG … #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK … #define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF … #define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU … #define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK … #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK … #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK … #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK … #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK … #define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK … #define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU … static const unsigned long cpucl0_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_CPUCL0 */ PNAME(mout_pll_cpucl0_p) = …; PNAME(mout_cpucl0_switch_user_p) = …; PNAME(mout_cpucl0_dbg_user_p) = …; PNAME(mout_cpucl0_pll_p) = …; static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = …; static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = …; static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = …; static const struct samsung_div_clock cpucl0_div_clks[] __initconst = …; static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = …; /* * Each parameter is going to be written into the corresponding DIV register. So * the actual divider value for each parameter will be 1/(param+1). All these * parameters must be in the range of 0..15, as the divider range for all of * these DIV clocks is 1..16. The default values for these dividers is * (1, 3, 3, 1). */ #define E850_CPU_DIV0(aclk, atclk, pclkdbg, periphclk) … static const struct exynos_cpuclk_cfg_data exynos850_cluster_clk_d[] __initconst = …; static const struct samsung_cpu_clock cpucl0_cpu_clks[] __initconst = …; static const struct samsung_cmu_info cpucl0_cmu_info __initconst = …; static void __init exynos850_cmu_cpucl0_init(struct device_node *np) { … } /* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */ CLK_OF_DECLARE(exynos850_cmu_cpucl0, "samsung,exynos850-cmu-cpucl0", exynos850_cmu_cpucl0_init); /* ---- CMU_CPUCL1 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_CPUCL1 (0x10800000) */ #define PLL_LOCKTIME_PLL_CPUCL1 … #define PLL_CON0_PLL_CPUCL1 … #define PLL_CON1_PLL_CPUCL1 … #define PLL_CON3_PLL_CPUCL1 … #define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER … #define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER … #define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL … #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK … #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK … #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG … #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK … #define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF … #define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU … #define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK … #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK … #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK … #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK … #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK … #define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK … #define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU … static const unsigned long cpucl1_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_CPUCL0 */ PNAME(mout_pll_cpucl1_p) = …; PNAME(mout_cpucl1_switch_user_p) = …; PNAME(mout_cpucl1_dbg_user_p) = …; PNAME(mout_cpucl1_pll_p) = …; static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = …; static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = …; static const struct samsung_div_clock cpucl1_div_clks[] __initconst = …; static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = …; static const struct samsung_cpu_clock cpucl1_cpu_clks[] __initconst = …; static const struct samsung_cmu_info cpucl1_cmu_info __initconst = …; static void __init exynos850_cmu_cpucl1_init(struct device_node *np) { … } /* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */ CLK_OF_DECLARE(exynos850_cmu_cpucl1, "samsung,exynos850-cmu-cpucl1", exynos850_cmu_cpucl1_init); /* ---- CMU_G3D ------------------------------------------------------------- */ /* Register Offset definitions for CMU_G3D (0x11400000) */ #define PLL_LOCKTIME_PLL_G3D … #define PLL_CON0_PLL_G3D … #define PLL_CON3_PLL_G3D … #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER … #define CLK_CON_MUX_MUX_CLK_G3D_BUSD … #define CLK_CON_DIV_DIV_CLK_G3D_BUSP … #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK … #define CLK_CON_GAT_CLK_G3D_GPU_CLK … #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK … #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK … #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK … #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK … #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK … static const unsigned long g3d_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_G3D */ PNAME(mout_g3d_pll_p) = …; PNAME(mout_g3d_switch_user_p) = …; PNAME(mout_g3d_busd_p) = …; /* * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set * for that PLL by default, so set_rate operation would fail. */ static const struct samsung_pll_clock g3d_pll_clks[] __initconst = …; static const struct samsung_mux_clock g3d_mux_clks[] __initconst = …; static const struct samsung_div_clock g3d_div_clks[] __initconst = …; static const struct samsung_gate_clock g3d_gate_clks[] __initconst = …; static const struct samsung_cmu_info g3d_cmu_info __initconst = …; /* ---- CMU_HSI ------------------------------------------------------------- */ /* Register Offset definitions for CMU_HSI (0x13400000) */ #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER … #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER … #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER … #define CLK_CON_MUX_MUX_CLK_HSI_RTC … #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK … #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV … #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 … #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 … #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK … #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK … #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN … #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK … #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK … #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK … #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 … #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY … static const unsigned long hsi_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_HSI */ PNAME(mout_hsi_bus_user_p) = …; PNAME(mout_hsi_mmc_card_user_p) = …; PNAME(mout_hsi_usb20drd_user_p) = …; PNAME(mout_hsi_rtc_p) = …; static const struct samsung_mux_clock hsi_mux_clks[] __initconst = …; static const struct samsung_gate_clock hsi_gate_clks[] __initconst = …; static const struct samsung_cmu_info hsi_cmu_info __initconst = …; /* ---- CMU_IS -------------------------------------------------------------- */ #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER … #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER … #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER … #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER … #define CLK_CON_DIV_DIV_CLK_IS_BUSP … #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK … #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK … #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK … #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK … #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK … #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA … #define CLK_CON_GAT_GOUT_IS_CLK_GDC … #define CLK_CON_GAT_GOUT_IS_CLK_IPP … #define CLK_CON_GAT_GOUT_IS_CLK_ITP … #define CLK_CON_GAT_GOUT_IS_CLK_MCSC … #define CLK_CON_GAT_GOUT_IS_CLK_VRA … #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK … #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK … #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK … #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK … #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 … #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 … #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK … static const unsigned long is_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_IS */ PNAME(mout_is_bus_user_p) = …; PNAME(mout_is_itp_user_p) = …; PNAME(mout_is_vra_user_p) = …; PNAME(mout_is_gdc_user_p) = …; static const struct samsung_mux_clock is_mux_clks[] __initconst = …; static const struct samsung_div_clock is_div_clks[] __initconst = …; static const struct samsung_gate_clock is_gate_clks[] __initconst = …; static const struct samsung_cmu_info is_cmu_info __initconst = …; /* ---- CMU_MFCMSCL --------------------------------------------------------- */ #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER … #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER … #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER … #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER … #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP … #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK … #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK … #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK … #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK … #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK … #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK … #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK … #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK … #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 … #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK … static const unsigned long mfcmscl_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_MFCMSCL */ PNAME(mout_mfcmscl_mfc_user_p) = …; PNAME(mout_mfcmscl_m2m_user_p) = …; PNAME(mout_mfcmscl_mcsc_user_p) = …; PNAME(mout_mfcmscl_jpeg_user_p) = …; static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = …; static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = …; static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = …; static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = …; /* ---- CMU_PERI ------------------------------------------------------------ */ /* Register Offset definitions for CMU_PERI (0x10030000) */ #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER … #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER … #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER … #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER … #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 … #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 … #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 … #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 … #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 … #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 … #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 … #define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK … #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK … #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK … #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK … #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK … #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK … #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK … #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK … #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK … #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK … #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK … #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK … #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK … #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK … #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK … #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK … #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK … #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK … #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK … #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK … #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK … #define CLK_CON_GAT_GOUT_PERI_UART_PCLK … #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK … #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK … static const unsigned long peri_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_PERI */ PNAME(mout_peri_bus_user_p) = …; PNAME(mout_peri_uart_user_p) = …; PNAME(mout_peri_hsi2c_user_p) = …; PNAME(mout_peri_spi_user_p) = …; static const struct samsung_mux_clock peri_mux_clks[] __initconst = …; static const struct samsung_div_clock peri_div_clks[] __initconst = …; static const struct samsung_gate_clock peri_gate_clks[] __initconst = …; static const struct samsung_cmu_info peri_cmu_info __initconst = …; static void __init exynos850_cmu_peri_init(struct device_node *np) { … } /* Register CMU_PERI early, as it's needed for MCT timer */ CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", exynos850_cmu_peri_init); /* ---- CMU_CORE ------------------------------------------------------------ */ /* Register Offset definitions for CMU_CORE (0x12000000) */ #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER … #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER … #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER … #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER … #define CLK_CON_MUX_MUX_CLK_CORE_GIC … #define CLK_CON_DIV_DIV_CLK_CORE_BUSP … #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK … #define CLK_CON_GAT_GOUT_CORE_GIC_CLK … #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK … #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK … #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN … #define CLK_CON_GAT_GOUT_CORE_PDMA_ACLK … #define CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK … #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK … #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK … #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK … static const unsigned long core_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_CORE */ PNAME(mout_core_bus_user_p) = …; PNAME(mout_core_cci_user_p) = …; PNAME(mout_core_mmc_embd_user_p) = …; PNAME(mout_core_sss_user_p) = …; PNAME(mout_core_gic_p) = …; static const struct samsung_mux_clock core_mux_clks[] __initconst = …; static const struct samsung_div_clock core_div_clks[] __initconst = …; static const struct samsung_gate_clock core_gate_clks[] __initconst = …; static const struct samsung_cmu_info core_cmu_info __initconst = …; /* ---- CMU_DPU ------------------------------------------------------------- */ /* Register Offset definitions for CMU_DPU (0x13000000) */ #define PLL_CON0_MUX_CLKCMU_DPU_USER … #define CLK_CON_DIV_DIV_CLK_DPU_BUSP … #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK … #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 … #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA … #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP … #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK … #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK … #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK … #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK … static const unsigned long dpu_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_DPU */ PNAME(mout_dpu_user_p) = …; static const struct samsung_mux_clock dpu_mux_clks[] __initconst = …; static const struct samsung_div_clock dpu_div_clks[] __initconst = …; static const struct samsung_gate_clock dpu_gate_clks[] __initconst = …; static const struct samsung_cmu_info dpu_cmu_info __initconst = …; /* ---- platform_driver ----------------------------------------------------- */ static int __init exynos850_cmu_probe(struct platform_device *pdev) { … } static const struct of_device_id exynos850_cmu_of_match[] = …; static struct platform_driver exynos850_cmu_driver __refdata = …; static int __init exynos850_cmu_init(void) { … } core_initcall(exynos850_cmu_init);
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