// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2022 Samsung Electronics Co., Ltd. * Author: Chanho Park <[email protected]> * * Common Clock Framework support for ExynosAuto V9 SoC. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/samsung,exynosautov9.h> #include "clk.h" #include "clk-exynos-arm64.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP … #define CLKS_NR_BUSMC … #define CLKS_NR_CORE … #define CLKS_NR_DPUM … #define CLKS_NR_FSYS0 … #define CLKS_NR_FSYS1 … #define CLKS_NR_FSYS2 … #define CLKS_NR_PERIC0 … #define CLKS_NR_PERIC1 … #define CLKS_NR_PERIS … /* ---- CMU_TOP ------------------------------------------------------------ */ /* Register Offset definitions for CMU_TOP (0x1b240000) */ #define PLL_LOCKTIME_PLL_SHARED0 … #define PLL_LOCKTIME_PLL_SHARED1 … #define PLL_LOCKTIME_PLL_SHARED2 … #define PLL_LOCKTIME_PLL_SHARED3 … #define PLL_LOCKTIME_PLL_SHARED4 … #define PLL_CON0_PLL_SHARED0 … #define PLL_CON3_PLL_SHARED0 … #define PLL_CON0_PLL_SHARED1 … #define PLL_CON3_PLL_SHARED1 … #define PLL_CON0_PLL_SHARED2 … #define PLL_CON3_PLL_SHARED2 … #define PLL_CON0_PLL_SHARED3 … #define PLL_CON3_PLL_SHARED3 … #define PLL_CON0_PLL_SHARED4 … #define PLL_CON3_PLL_SHARED4 … /* MUX */ #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS … #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS … #define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS … #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU … #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS … #define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS … #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST … #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS … #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC … #define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS … #define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS … #define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS … #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS … #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE … #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS … #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD … #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD … #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS … #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET … #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD … #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D … #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL … #define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS … #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC … #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD … #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP … #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS … #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS … #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP … #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS … #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP … #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS … #define CLK_CON_MUX_MUX_CMU_CMUREF … /* DIV */ #define CLK_CON_DIV_CLKCMU_ACC_BUS … #define CLK_CON_DIV_CLKCMU_APM_BUS … #define CLK_CON_DIV_CLKCMU_AUD_BUS … #define CLK_CON_DIV_CLKCMU_AUD_CPU … #define CLK_CON_DIV_CLKCMU_BUSC_BUS … #define CLK_CON_DIV_CLKCMU_BUSMC_BUS … #define CLK_CON_DIV_CLKCMU_CORE_BUS … #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER … #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER … #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_DIV_CLKCMU_DPTX_BUS … #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC … #define CLK_CON_DIV_CLKCMU_DPUM_BUS … #define CLK_CON_DIV_CLKCMU_DPUS0_BUS … #define CLK_CON_DIV_CLKCMU_DPUS1_BUS … #define CLK_CON_DIV_CLKCMU_FSYS0_BUS … #define CLK_CON_DIV_CLKCMU_FSYS0_PCIE … #define CLK_CON_DIV_CLKCMU_FSYS1_BUS … #define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD … #define CLK_CON_DIV_CLKCMU_FSYS2_BUS … #define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET … #define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD … #define CLK_CON_DIV_CLKCMU_G2D_G2D … #define CLK_CON_DIV_CLKCMU_G2D_MSCL … #define CLK_CON_DIV_CLKCMU_G3D00_SWITCH … #define CLK_CON_DIV_CLKCMU_G3D01_SWITCH … #define CLK_CON_DIV_CLKCMU_G3D1_SWITCH … #define CLK_CON_DIV_CLKCMU_ISPB_BUS … #define CLK_CON_DIV_CLKCMU_MFC_MFC … #define CLK_CON_DIV_CLKCMU_MFC_WFD … #define CLK_CON_DIV_CLKCMU_MIF_BUSP … #define CLK_CON_DIV_CLKCMU_NPU_BUS … #define CLK_CON_DIV_CLKCMU_PERIC0_BUS … #define CLK_CON_DIV_CLKCMU_PERIC0_IP … #define CLK_CON_DIV_CLKCMU_PERIC1_BUS … #define CLK_CON_DIV_CLKCMU_PERIC1_IP … #define CLK_CON_DIV_CLKCMU_PERIS_BUS … #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST … #define CLK_CON_DIV_PLL_SHARED0_DIV2 … #define CLK_CON_DIV_PLL_SHARED0_DIV3 … #define CLK_CON_DIV_PLL_SHARED1_DIV2 … #define CLK_CON_DIV_PLL_SHARED1_DIV3 … #define CLK_CON_DIV_PLL_SHARED1_DIV4 … #define CLK_CON_DIV_PLL_SHARED2_DIV2 … #define CLK_CON_DIV_PLL_SHARED2_DIV3 … #define CLK_CON_DIV_PLL_SHARED2_DIV4 … #define CLK_CON_DIV_PLL_SHARED4_DIV2 … #define CLK_CON_DIV_PLL_SHARED4_DIV4 … /* GATE */ #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST … #define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST … #define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST … #define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST … #define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST … #define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST … #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD … #define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS … #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS … #define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS … #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU … #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS … #define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS … #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST … #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER … #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS … #define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC … #define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS … #define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS … #define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS … #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS … #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE … #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS … #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD … #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS … #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET … #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD … #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D … #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL … #define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH … #define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS … #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC … #define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD … #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP … #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS … #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS … #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP … #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS … #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP … #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS … static const unsigned long top_clk_regs[] __initconst = …; static const struct samsung_pll_clock top_pll_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_TOP */ PNAME(mout_shared0_pll_p) = …; PNAME(mout_shared1_pll_p) = …; PNAME(mout_shared2_pll_p) = …; PNAME(mout_shared3_pll_p) = …; PNAME(mout_shared4_pll_p) = …; PNAME(mout_clkcmu_cmu_boost_p) = …; PNAME(mout_clkcmu_cmu_cmuref_p) = …; PNAME(mout_clkcmu_acc_bus_p) = …; PNAME(mout_clkcmu_apm_bus_p) = …; PNAME(mout_clkcmu_aud_cpu_p) = …; PNAME(mout_clkcmu_aud_bus_p) = …; PNAME(mout_clkcmu_busc_bus_p) = …; PNAME(mout_clkcmu_core_bus_p) = …; PNAME(mout_clkcmu_cpucl0_switch_p) = …; PNAME(mout_clkcmu_cpucl0_cluster_p) = …; PNAME(mout_clkcmu_dptx_bus_p) = …; PNAME(mout_clkcmu_dptx_dpgtc_p) = …; PNAME(mout_clkcmu_dpum_bus_p) = …; PNAME(mout_clkcmu_fsys0_bus_p) = …; PNAME(mout_clkcmu_fsys0_pcie_p) = …; PNAME(mout_clkcmu_fsys1_bus_p) = …; PNAME(mout_clkcmu_fsys1_usbdrd_p) = …; PNAME(mout_clkcmu_fsys1_mmc_card_p) = …; PNAME(mout_clkcmu_fsys2_ethernet_p) = …; PNAME(mout_clkcmu_g2d_g2d_p) = …; PNAME(mout_clkcmu_g3d0_switch_p) = …; PNAME(mout_clkcmu_g3d1_switch_p) = …; PNAME(mout_clkcmu_mif_switch_p) = …; PNAME(mout_clkcmu_npu_bus_p) = …; PNAME(mout_clkcmu_peric0_bus_p) = …; static const struct samsung_mux_clock top_mux_clks[] __initconst = …; static const struct samsung_div_clock top_div_clks[] __initconst = …; static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = …; static const struct samsung_gate_clock top_gate_clks[] __initconst = …; static const struct samsung_cmu_info top_cmu_info __initconst = …; static void __init exynosautov9_cmu_top_init(struct device_node *np) { … } /* Register CMU_TOP early, as it's a dependency for other early domains */ CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top", exynosautov9_cmu_top_init); /* ---- CMU_BUSMC ---------------------------------------------------------- */ /* Register Offset definitions for CMU_BUSMC (0x1b200000) */ #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER … #define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP … #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK … static const unsigned long busmc_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_BUSMC */ PNAME(mout_busmc_bus_user_p) = …; static const struct samsung_mux_clock busmc_mux_clks[] __initconst = …; static const struct samsung_div_clock busmc_div_clks[] __initconst = …; static const struct samsung_gate_clock busmc_gate_clks[] __initconst = …; static const struct samsung_cmu_info busmc_cmu_info __initconst = …; /* ---- CMU_CORE ----------------------------------------------------------- */ /* Register Offset definitions for CMU_CORE (0x1b030000) */ #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER … #define CLK_CON_MUX_MUX_CORE_CMUREF … #define CLK_CON_DIV_DIV_CLK_CORE_BUSP … #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK … #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK … #define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK … static const unsigned long core_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_CORE */ PNAME(mout_core_bus_user_p) = …; static const struct samsung_mux_clock core_mux_clks[] __initconst = …; static const struct samsung_div_clock core_div_clks[] __initconst = …; static const struct samsung_gate_clock core_gate_clks[] __initconst = …; static const struct samsung_cmu_info core_cmu_info __initconst = …; /* ---- CMU_DPUM ---------------------------------------------------------- */ /* Register Offset definitions for CMU_DPUM (0x18c00000) */ #define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER … #define CLK_CON_DIV_DIV_CLK_DPUM_BUSP … #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON … #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA … #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP … #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1 … #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1 … #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1 … #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1 … static const unsigned long dpum_clk_regs[] __initconst = …; PNAME(mout_dpum_bus_user_p) = …; static const struct samsung_mux_clock dpum_mux_clks[] __initconst = …; static const struct samsung_div_clock dpum_div_clks[] __initconst = …; static const struct samsung_gate_clock dpum_gate_clks[] __initconst = …; static const struct samsung_cmu_info dpum_cmu_info __initconst = …; /* ---- CMU_FSYS0 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS2 (0x17700000) */ #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER … #define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER … #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK … #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN … #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN … #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN … #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN … #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN … #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK … #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK … static const unsigned long fsys0_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_FSYS0 */ PNAME(mout_fsys0_bus_user_p) = …; PNAME(mout_fsys0_pcie_user_p) = …; static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = …; static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = …; static const struct samsung_cmu_info fsys0_cmu_info __initconst = …; /* ---- CMU_FSYS1 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS1 (0x17040000) */ #define PLL_LOCKTIME_PLL_MMC … #define PLL_CON0_PLL_MMC … #define PLL_CON3_PLL_MMC … #define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER … #define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER … #define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER … #define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD … #define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK … static const unsigned long fsys1_clk_regs[] __initconst = …; static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_FSYS1 */ PNAME(mout_fsys1_bus_user_p) = …; PNAME(mout_fsys1_mmc_pll_p) = …; PNAME(mout_fsys1_mmc_card_user_p) = …; PNAME(mout_fsys1_usbdrd_user_p) = …; PNAME(mout_fsys1_mmc_card_p) = …; static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = …; static const struct samsung_div_clock fsys1_div_clks[] __initconst = …; static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = …; static const struct samsung_cmu_info fsys1_cmu_info __initconst = …; /* ---- CMU_FSYS2 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */ #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER … #define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER … #define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER … #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO … #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK … #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO … static const unsigned long fsys2_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_FSYS2 */ PNAME(mout_fsys2_bus_user_p) = …; PNAME(mout_fsys2_ufs_embd_user_p) = …; PNAME(mout_fsys2_ethernet_user_p) = …; static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = …; static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = …; static const struct samsung_cmu_info fsys2_cmu_info __initconst = …; /* ---- CMU_PERIC0 --------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIC0 (0x10200000) */ #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 … #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 … static const unsigned long peric0_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_PERIC0 */ PNAME(mout_peric0_bus_user_p) = …; PNAME(mout_peric0_ip_user_p) = …; PNAME(mout_peric0_usi_p) = …; static const struct samsung_mux_clock peric0_mux_clks[] __initconst = …; static const struct samsung_div_clock peric0_div_clks[] __initconst = …; static const struct samsung_gate_clock peric0_gate_clks[] __initconst = …; static const struct samsung_cmu_info peric0_cmu_info __initconst = …; /* ---- CMU_PERIC1 --------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIC1 (0x10800000) */ #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER … #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER … #define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI … #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI … #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI … #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI … #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI … #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI … #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI … #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 … #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 … static const unsigned long peric1_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_PERIC1 */ PNAME(mout_peric1_bus_user_p) = …; PNAME(mout_peric1_ip_user_p) = …; PNAME(mout_peric1_usi_p) = …; static const struct samsung_mux_clock peric1_mux_clks[] __initconst = …; static const struct samsung_div_clock peric1_div_clks[] __initconst = …; static const struct samsung_gate_clock peric1_gate_clks[] __initconst = …; static const struct samsung_cmu_info peric1_cmu_info __initconst = …; /* ---- CMU_PERIS ---------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIS (0x10020000) */ #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER … #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK … #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK … static const unsigned long peris_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_PERIS */ PNAME(mout_peris_bus_user_p) = …; static const struct samsung_mux_clock peris_mux_clks[] __initconst = …; static const struct samsung_gate_clock peris_gate_clks[] __initconst = …; static const struct samsung_cmu_info peris_cmu_info __initconst = …; static int __init exynosautov9_cmu_probe(struct platform_device *pdev) { … } static const struct of_device_id exynosautov9_cmu_of_match[] = …; static struct platform_driver exynosautov9_cmu_driver __refdata = …; static int __init exynosautov9_cmu_init(void) { … } core_initcall(exynosautov9_cmu_init);
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