// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Author: Mateusz Krawczuk <[email protected]> * * Based on clock drivers for S3C64xx and Exynos4 SoCs. * * Common Clock Framework support for all S5PC110/S5PV210 SoCs. */ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> #include "clk.h" #include "clk-pll.h" #include <dt-bindings/clock/s5pv210.h> /* S5PC110/S5PV210 clock controller register offsets */ #define APLL_LOCK … #define MPLL_LOCK … #define EPLL_LOCK … #define VPLL_LOCK … #define APLL_CON0 … #define APLL_CON1 … #define MPLL_CON … #define EPLL_CON0 … #define EPLL_CON1 … #define VPLL_CON … #define CLK_SRC0 … #define CLK_SRC1 … #define CLK_SRC2 … #define CLK_SRC3 … #define CLK_SRC4 … #define CLK_SRC5 … #define CLK_SRC6 … #define CLK_SRC_MASK0 … #define CLK_SRC_MASK1 … #define CLK_DIV0 … #define CLK_DIV1 … #define CLK_DIV2 … #define CLK_DIV3 … #define CLK_DIV4 … #define CLK_DIV5 … #define CLK_DIV6 … #define CLK_DIV7 … #define CLK_GATE_MAIN0 … #define CLK_GATE_MAIN1 … #define CLK_GATE_MAIN2 … #define CLK_GATE_PERI0 … #define CLK_GATE_PERI1 … #define CLK_GATE_SCLK0 … #define CLK_GATE_SCLK1 … #define CLK_GATE_IP0 … #define CLK_GATE_IP1 … #define CLK_GATE_IP2 … #define CLK_GATE_IP3 … #define CLK_GATE_IP4 … #define CLK_GATE_BLOCK … #define CLK_GATE_IP5 … #define CLK_OUT … #define MISC … #define OM_STAT … /* IDs of PLLs available on S5PV210/S5P6442 SoCs */ enum { … }; /* IDs of external clocks (used for legacy boards) */ enum { … }; static void __iomem *reg_base; /* List of registers that need to be preserved across suspend/resume. */ static unsigned long s5pv210_clk_regs[] __initdata = …; /* Mux parent lists. */ static const char *const fin_pll_p[] __initconst = …; static const char *const mout_apll_p[] __initconst = …; static const char *const mout_mpll_p[] __initconst = …; static const char *const mout_epll_p[] __initconst = …; static const char *const mout_vpllsrc_p[] __initconst = …; static const char *const mout_vpll_p[] __initconst = …; static const char *const mout_group1_p[] __initconst = …; static const char *const mout_group2_p[] __initconst = …; static const char *const mout_audio0_p[] __initconst = …; static const char *const mout_audio1_p[] __initconst = …; static const char *const mout_audio2_p[] __initconst = …; static const char *const mout_spdif_p[] __initconst = …; static const char *const mout_group3_p[] __initconst = …; static const char *const mout_group4_p[] __initconst = …; static const char *const mout_flash_p[] __initconst = …; static const char *const mout_dac_p[] __initconst = …; static const char *const mout_hdmi_p[] __initconst = …; static const char *const mout_mixer_p[] __initconst = …; static const char *const mout_vpll_6442_p[] __initconst = …; static const char *const mout_mixer_6442_p[] __initconst = …; static const char *const mout_d0sync_6442_p[] __initconst = …; static const char *const mout_d1sync_6442_p[] __initconst = …; static const char *const mout_group2_6442_p[] __initconst = …; static const char *const mout_audio0_6442_p[] __initconst = …; static const char *const mout_audio1_6442_p[] __initconst = …; static const char *const mout_clksel_p[] __initconst = …; static const char *const mout_clksel_6442_p[] __initconst = …; static const char *const mout_clkout_p[] __initconst = …; /* Common fixed factor clocks. */ static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = …; /* PLL input mux (fin_pll), which needs to be registered before PLLs. */ static const struct samsung_mux_clock early_mux_clks[] __initconst = …; /* Common clock muxes. */ static const struct samsung_mux_clock mux_clks[] __initconst = …; /* S5PV210-specific clock muxes. */ static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = …; /* S5P6442-specific clock muxes. */ static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = …; /* S5PV210-specific fixed rate clocks generated inside the SoC. */ static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = …; /* S5P6442-specific fixed rate clocks generated inside the SoC. */ static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = …; /* Common clock dividers. */ static const struct samsung_div_clock div_clks[] __initconst = …; /* S5PV210-specific clock dividers. */ static const struct samsung_div_clock s5pv210_div_clks[] __initconst = …; /* S5P6442-specific clock dividers. */ static const struct samsung_div_clock s5p6442_div_clks[] __initconst = …; /* Common clock gates. */ static const struct samsung_gate_clock gate_clks[] __initconst = …; /* S5PV210-specific clock gates. */ static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = …; /* S5P6442-specific clock gates. */ static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = …; /* * Clock aliases for legacy clkdev look-up. * NOTE: Needed only to support legacy board files. */ static const struct samsung_clock_alias s5pv210_aliases[] __initconst = …; /* S5PV210-specific PLLs. */ static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = …; /* S5P6442-specific PLLs. */ static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = …; static void __init __s5pv210_clk_init(struct device_node *np, unsigned long xxti_f, unsigned long xusbxti_f, bool is_s5p6442) { … } static void __init s5pv210_clk_dt_init(struct device_node *np) { … } CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init); static void __init s5p6442_clk_dt_init(struct device_node *np) { … } CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init);
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