linux/drivers/clk/socfpga/clk.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2013, Steffen Trumtrar <[email protected]>
 *
 * based on drivers/clk/tegra/clk.h
 */

#ifndef __SOCFPGA_CLK_H
#define __SOCFPGA_CLK_H

#include <linux/clk-provider.h>

/* Clock Manager offsets */
#define CLKMGR_CTRL …
#define CLKMGR_BYPASS …
#define CLKMGR_DBCTRL …
#define CLKMGR_L4SRC …
#define CLKMGR_PERPLL_SRC …

#define SOCFPGA_MAX_PARENTS …

#define streq(a, b) …
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) …

#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) …

extern void __iomem *clk_mgr_base_addr;
extern void __iomem *clk_mgr_a10_base_addr;

void __init socfpga_pll_init(struct device_node *node);
void __init socfpga_periph_init(struct device_node *node);
void __init socfpga_gate_init(struct device_node *node);
void socfpga_a10_pll_init(struct device_node *node);
void socfpga_a10_periph_init(struct device_node *node);
void socfpga_a10_gate_init(struct device_node *node);

struct socfpga_pll { … };

struct socfpga_gate_clk { … };

struct socfpga_periph_clk { … };

#endif /* SOCFPGA_CLK_H */