// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. * https://www.samsung.com * Copyright (c) 2017-2022 Tesla, Inc. * https://www.tesla.com * * Common Clock Framework support for FSD SoC. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/fsd-clk.h> #include "clk.h" #include "clk-exynos-arm64.h" /* Register Offset definitions for CMU_CMU (0x11c10000) */ #define PLL_LOCKTIME_PLL_SHARED0 … #define PLL_LOCKTIME_PLL_SHARED1 … #define PLL_LOCKTIME_PLL_SHARED2 … #define PLL_LOCKTIME_PLL_SHARED3 … #define PLL_CON0_PLL_SHARED0 … #define PLL_CON0_PLL_SHARED1 … #define PLL_CON0_PLL_SHARED2 … #define PLL_CON0_PLL_SHARED3 … #define MUX_CMU_CIS0_CLKMUX … #define MUX_CMU_CIS1_CLKMUX … #define MUX_CMU_CIS2_CLKMUX … #define MUX_CMU_CPUCL_SWITCHMUX … #define MUX_CMU_FSYS1_ACLK_MUX … #define MUX_PLL_SHARED0_MUX … #define MUX_PLL_SHARED1_MUX … #define DIV_CMU_CIS0_CLK … #define DIV_CMU_CIS1_CLK … #define DIV_CMU_CIS2_CLK … #define DIV_CMU_CMU_ACLK … #define DIV_CMU_CPUCL_SWITCH … #define DIV_CMU_FSYS0_SHARED0DIV4 … #define DIV_CMU_FSYS0_SHARED1DIV3 … #define DIV_CMU_FSYS0_SHARED1DIV4 … #define DIV_CMU_FSYS1_SHARED0DIV4 … #define DIV_CMU_FSYS1_SHARED0DIV8 … #define DIV_CMU_IMEM_ACLK … #define DIV_CMU_IMEM_DMACLK … #define DIV_CMU_IMEM_TCUCLK … #define DIV_CMU_PERIC_SHARED0DIV20 … #define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK … #define DIV_CMU_PERIC_SHARED1DIV36 … #define DIV_CMU_PERIC_SHARED1DIV4_DMACLK … #define DIV_PLL_SHARED0_DIV2 … #define DIV_PLL_SHARED0_DIV3 … #define DIV_PLL_SHARED0_DIV4 … #define DIV_PLL_SHARED0_DIV6 … #define DIV_PLL_SHARED1_DIV3 … #define DIV_PLL_SHARED1_DIV36 … #define DIV_PLL_SHARED1_DIV4 … #define DIV_PLL_SHARED1_DIV9 … #define GAT_CMU_CIS0_CLKGATE … #define GAT_CMU_CIS1_CLKGATE … #define GAT_CMU_CIS2_CLKGATE … #define GAT_CMU_CPUCL_SWITCH_GATE … #define GAT_CMU_FSYS0_SHARED0DIV4_GATE … #define GAT_CMU_FSYS0_SHARED1DIV4_CLK … #define GAT_CMU_FSYS0_SHARED1DIV4_GATE … #define GAT_CMU_FSYS1_SHARED0DIV4_GATE … #define GAT_CMU_FSYS1_SHARED1DIV4_GATE … #define GAT_CMU_IMEM_ACLK_GATE … #define GAT_CMU_IMEM_DMACLK_GATE … #define GAT_CMU_IMEM_TCUCLK_GATE … #define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE … #define GAT_CMU_PERIC_SHARED0DIVE4_GATE … #define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE … #define GAT_CMU_PERIC_SHARED1DIVE4_GATE … #define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK … #define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK … #define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU … #define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK … static const unsigned long cmu_clk_regs[] __initconst = …; static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = …; static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = …; static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = …; static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = …; static const struct samsung_pll_clock cmu_pll_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_CMU */ PNAME(mout_cmu_shared0_pll_p) = …; PNAME(mout_cmu_shared1_pll_p) = …; PNAME(mout_cmu_shared2_pll_p) = …; PNAME(mout_cmu_shared3_pll_p) = …; PNAME(mout_cmu_cis0_clkmux_p) = …; PNAME(mout_cmu_cis1_clkmux_p) = …; PNAME(mout_cmu_cis2_clkmux_p) = …; PNAME(mout_cmu_cpucl_switchmux_p) = …; PNAME(mout_cmu_fsys1_aclk_mux_p) = …; PNAME(mout_cmu_pll_shared0_mux_p) = …; PNAME(mout_cmu_pll_shared1_mux_p) = …; static const struct samsung_mux_clock cmu_mux_clks[] __initconst = …; static const struct samsung_div_clock cmu_div_clks[] __initconst = …; static const struct samsung_gate_clock cmu_gate_clks[] __initconst = …; static const struct samsung_cmu_info cmu_cmu_info __initconst = …; static void __init fsd_clk_cmu_init(struct device_node *np) { … } CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init); /* Register Offset definitions for CMU_PERIC (0x14010000) */ #define PLL_CON0_PERIC_DMACLK_MUX … #define PLL_CON0_PERIC_EQOS_BUSCLK_MUX … #define PLL_CON0_PERIC_PCLK_MUX … #define PLL_CON0_PERIC_TBUCLK_MUX … #define PLL_CON0_SPI_CLK … #define PLL_CON0_SPI_PCLK … #define PLL_CON0_UART_CLK … #define PLL_CON0_UART_PCLK … #define MUX_PERIC_EQOS_PHYRXCLK … #define DIV_EQOS_BUSCLK … #define DIV_PERIC_MCAN_CLK … #define DIV_RGMII_CLK … #define DIV_RII_CLK … #define DIV_RMII_CLK … #define DIV_SPI_CLK … #define DIV_UART_CLK … #define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I … #define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK … #define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK … #define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK … #define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK … #define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK … #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM … #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS … #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM … #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS … #define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK … #define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK … #define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK … #define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK … #define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK … #define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK … #define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK … #define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK … #define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK … #define GAT_EQOS_TOP_IPCLKPORT_ACLK_I … #define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I … #define GAT_EQOS_TOP_IPCLKPORT_HCLK_I … #define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I … #define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I … #define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I … #define GAT_GPIO_PERIC_IPCLKPORT_PCLK … #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D … #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P … #define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 … #define GAT_PERIC_DMA0_IPCLKPORT_ACLK … #define GAT_PERIC_DMA1_IPCLKPORT_ACLK … #define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK … #define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK … #define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK … #define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK … #define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK … #define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK … #define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK … #define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK … #define GAT_PERIC_MCAN0_IPCLKPORT_CCLK … #define GAT_PERIC_MCAN0_IPCLKPORT_PCLK … #define GAT_PERIC_MCAN1_IPCLKPORT_CCLK … #define GAT_PERIC_MCAN1_IPCLKPORT_PCLK … #define GAT_PERIC_MCAN2_IPCLKPORT_CCLK … #define GAT_PERIC_MCAN2_IPCLKPORT_PCLK … #define GAT_PERIC_MCAN3_IPCLKPORT_CCLK … #define GAT_PERIC_MCAN3_IPCLKPORT_PCLK … #define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 … #define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 … #define GAT_PERIC_SMMU_IPCLKPORT_CCLK … #define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK … #define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK … #define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI … #define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK … #define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI … #define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK … #define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI … #define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M … #define GAT_PERIC_TDM0_IPCLKPORT_PCLK … #define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M … #define GAT_PERIC_TDM1_IPCLKPORT_PCLK … #define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART … #define GAT_PERIC_UART0_IPCLKPORT_PCLK … #define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART … #define GAT_PERIC_UART1_IPCLKPORT_PCLK … #define GAT_SYSREG_PERI_IPCLKPORT_PCLK … static const unsigned long peric_clk_regs[] __initconst = …; static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_PERIC */ PNAME(mout_peric_dmaclk_p) = …; PNAME(mout_peric_eqos_busclk_p) = …; PNAME(mout_peric_pclk_p) = …; PNAME(mout_peric_tbuclk_p) = …; PNAME(mout_peric_spi_clk_p) = …; PNAME(mout_peric_spi_pclk_p) = …; PNAME(mout_peric_uart_clk_p) = …; PNAME(mout_peric_uart_pclk_p) = …; PNAME(mout_peric_eqos_phyrxclk_p) = …; static const struct samsung_mux_clock peric_mux_clks[] __initconst = …; static const struct samsung_div_clock peric_div_clks[] __initconst = …; static const struct samsung_gate_clock peric_gate_clks[] __initconst = …; static const struct samsung_cmu_info peric_cmu_info __initconst = …; /* Register Offset definitions for CMU_FSYS0 (0x15010000) */ #define PLL_CON0_CLKCMU_FSYS0_UNIPRO … #define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK … #define PLL_CON0_EQOS_RGMII_125_MUX1 … #define DIV_CLK_UNIPRO … #define DIV_EQS_RGMII_CLK_125 … #define DIV_PERIBUS_GRP … #define DIV_EQOS_RII_CLK2O5 … #define DIV_EQOS_RMIICLK_25 … #define DIV_PCIE_PHY_OSCCLK … #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I … #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I … #define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK … #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC … #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 … #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 … #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 … #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 … #define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK … #define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK … #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK … #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK … #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK … #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK … #define GAT_FSYS0_CPE425_IPCLKPORT_ACLK … #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I … #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I … #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I … #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I … #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I … #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK … #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D … #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 … #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P … #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC … #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC … #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK … #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK … #define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK … #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS … #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK … #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO … #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK … #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS … #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK … #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO … #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK … #define GAT_FSYS0_RII_CLK_DIVGATE … static const unsigned long fsys0_clk_regs[] __initconst = …; static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_FSYS0 */ PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = …; PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = …; PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = …; static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = …; static const struct samsung_div_clock fsys0_div_clks[] __initconst = …; static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = …; static const struct samsung_cmu_info fsys0_cmu_info __initconst = …; /* Register Offset definitions for CMU_FSYS1 (0x16810000) */ #define PLL_CON0_ACLK_FSYS1_BUSP_MUX … #define PLL_CON0_PCLKL_FSYS1_BUSP_MUX … #define DIV_CLK_FSYS1_PHY0_OSCCLK … #define DIV_CLK_FSYS1_PHY1_OSCCLK … #define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK … #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK … #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK … #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK … #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL … #define GAT_FSYS1_PHY0_OSCCLLK … #define GAT_FSYS1_PHY1_OSCCLK … #define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK … #define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK … #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK … #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK … #define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK … #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 … #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 … #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK … #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK … #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK … #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK … #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK … #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK … #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK … #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK … #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK … #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK … #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL … #define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK … #define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK … static const unsigned long fsys1_clk_regs[] __initconst = …; static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_FSYS1 */ PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = …; PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = …; static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = …; static const struct samsung_div_clock fsys1_div_clks[] __initconst = …; static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = …; static const struct samsung_cmu_info fsys1_cmu_info __initconst = …; /* Register Offset definitions for CMU_IMEM (0x10010000) */ #define PLL_CON0_CLK_IMEM_ACLK … #define PLL_CON0_CLK_IMEM_INTMEMCLK … #define PLL_CON0_CLK_IMEM_TCUCLK … #define DIV_OSCCLK_IMEM_TMUTSCLK … #define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK … #define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO … #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK … #define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK … #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK … #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS … #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK … #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS … #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK … #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS … #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK … #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS … #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK … #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS … #define GAT_IMEM_WDT0_IPCLKPORT_CLK … #define GAT_IMEM_WDT1_IPCLKPORT_CLK … #define GAT_IMEM_WDT2_IPCLKPORT_CLK … #define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM … #define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM … #define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM … #define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS … #define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS … #define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS … #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM … #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS … #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM … #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS … #define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK … #define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK … #define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK … #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK … #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK … #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK … #define GAT_IMEM_DMA0_IPCLKPORT_ACLK … #define GAT_IMEM_DMA1_IPCLKPORT_ACLK … #define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK … #define GAT_IMEM_GIC_IPCLKPORT_CLK … #define GAT_IMEM_INTMEM_IPCLKPORT_ACLK … #define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK … #define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK … #define GAT_IMEM_MCT_IPCLKPORT_PCLK … #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D … #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU … #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P … #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK … #define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK … #define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK … #define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK … #define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK … #define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK … #define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK … #define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK … #define GAT_IMEM_TCU_IPCLKPORT_ACLK … #define GAT_IMEM_WDT0_IPCLKPORT_PCLK … #define GAT_IMEM_WDT1_IPCLKPORT_PCLK … #define GAT_IMEM_WDT2_IPCLKPORT_PCLK … static const unsigned long imem_clk_regs[] __initconst = …; PNAME(mout_imem_clk_imem_tcuclk_p) = …; PNAME(mout_imem_clk_imem_aclk_p) = …; PNAME(mout_imem_clk_imem_intmemclk_p) = …; static const struct samsung_mux_clock imem_mux_clks[] __initconst = …; static const struct samsung_div_clock imem_div_clks[] __initconst = …; static const struct samsung_gate_clock imem_gate_clks[] __initconst = …; static const struct samsung_cmu_info imem_cmu_info __initconst = …; static void __init fsd_clk_imem_init(struct device_node *np) { … } CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init); /* Register Offset definitions for CMU_MFC (0x12810000) */ #define PLL_LOCKTIME_PLL_MFC … #define PLL_CON0_PLL_MFC … #define MUX_MFC_BUSD … #define MUX_MFC_BUSP … #define DIV_MFC_BUSD_DIV4 … #define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK … #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM … #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS … #define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK … #define GAT_MFC_MFC_IPCLKPORT_ACLK … #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D … #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P … #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK … #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK … #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK … #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK … #define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK … #define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK … #define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK … #define GAT_MFC_BUSD_DIV4_GATE … #define GAT_MFC_BUSD_GATE … static const unsigned long mfc_clk_regs[] __initconst = …; static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = …; static const struct samsung_pll_clock mfc_pll_clks[] __initconst = …; PNAME(mout_mfc_pll_p) = …; PNAME(mout_mfc_busp_p) = …; PNAME(mout_mfc_busd_p) = …; static const struct samsung_mux_clock mfc_mux_clks[] __initconst = …; static const struct samsung_div_clock mfc_div_clks[] __initconst = …; static const struct samsung_gate_clock mfc_gate_clks[] __initconst = …; static const struct samsung_cmu_info mfc_cmu_info __initconst = …; /* Register Offset definitions for CMU_CAM_CSI (0x12610000) */ #define PLL_LOCKTIME_PLL_CAM_CSI … #define PLL_CON0_PLL_CAM_CSI … #define DIV_CAM_CSI0_ACLK … #define DIV_CAM_CSI1_ACLK … #define DIV_CAM_CSI2_ACLK … #define DIV_CAM_CSI_BUSD … #define DIV_CAM_CSI_BUSP … #define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK … #define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK … #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 … #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 … #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 … #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC … #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC … #define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK … #define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK … #define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK … #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D … #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P … #define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK … #define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK … static const unsigned long cam_csi_clk_regs[] __initconst = …; static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = …; static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = …; PNAME(mout_cam_csi_pll_p) = …; static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = …; static const struct samsung_div_clock cam_csi_div_clks[] __initconst = …; static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = …; static const struct samsung_cmu_info cam_csi_cmu_info __initconst = …; /** * fsd_cmu_probe - Probe function for FSD platform clocks * @pdev: Pointer to platform device * * Configure clock hierarchy for clock domains of FSD platform */ static int __init fsd_cmu_probe(struct platform_device *pdev) { … } /* CMUs which belong to Power Domains and need runtime PM to be implemented */ static const struct of_device_id fsd_cmu_of_match[] = …; static struct platform_driver fsd_cmu_driver __refdata = …; static int __init fsd_cmu_init(void) { … } core_initcall(fsd_cmu_init);
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