// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Chanwoo Choi <[email protected]> * * Common Clock Framework support for Exynos5433 SoC. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> #include <dt-bindings/clock/exynos5433.h> #include "clk.h" #include "clk-cpu.h" #include "clk-exynos-arm64.h" #include "clk-pll.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP … #define CLKS_NR_CPIF … #define CLKS_NR_MIF … #define CLKS_NR_PERIC … #define CLKS_NR_PERIS … #define CLKS_NR_FSYS … #define CLKS_NR_G2D … #define CLKS_NR_DISP … #define CLKS_NR_AUD … #define CLKS_NR_BUSX … #define CLKS_NR_G3D … #define CLKS_NR_GSCL … #define CLKS_NR_APOLLO … #define CLKS_NR_ATLAS … #define CLKS_NR_MSCL … #define CLKS_NR_MFC … #define CLKS_NR_HEVC … #define CLKS_NR_ISP … #define CLKS_NR_CAM0 … #define CLKS_NR_CAM1 … #define CLKS_NR_IMEM … /* * Register offset definitions for CMU_TOP */ #define ISP_PLL_LOCK … #define AUD_PLL_LOCK … #define ISP_PLL_CON0 … #define ISP_PLL_CON1 … #define ISP_PLL_FREQ_DET … #define AUD_PLL_CON0 … #define AUD_PLL_CON1 … #define AUD_PLL_CON2 … #define AUD_PLL_FREQ_DET … #define MUX_SEL_TOP0 … #define MUX_SEL_TOP1 … #define MUX_SEL_TOP2 … #define MUX_SEL_TOP3 … #define MUX_SEL_TOP4 … #define MUX_SEL_TOP_MSCL … #define MUX_SEL_TOP_CAM1 … #define MUX_SEL_TOP_DISP … #define MUX_SEL_TOP_FSYS0 … #define MUX_SEL_TOP_FSYS1 … #define MUX_SEL_TOP_PERIC0 … #define MUX_SEL_TOP_PERIC1 … #define MUX_ENABLE_TOP0 … #define MUX_ENABLE_TOP1 … #define MUX_ENABLE_TOP2 … #define MUX_ENABLE_TOP3 … #define MUX_ENABLE_TOP4 … #define MUX_ENABLE_TOP_MSCL … #define MUX_ENABLE_TOP_CAM1 … #define MUX_ENABLE_TOP_DISP … #define MUX_ENABLE_TOP_FSYS0 … #define MUX_ENABLE_TOP_FSYS1 … #define MUX_ENABLE_TOP_PERIC0 … #define MUX_ENABLE_TOP_PERIC1 … #define MUX_STAT_TOP0 … #define MUX_STAT_TOP1 … #define MUX_STAT_TOP2 … #define MUX_STAT_TOP3 … #define MUX_STAT_TOP4 … #define MUX_STAT_TOP_MSCL … #define MUX_STAT_TOP_CAM1 … #define MUX_STAT_TOP_FSYS0 … #define MUX_STAT_TOP_FSYS1 … #define MUX_STAT_TOP_PERIC0 … #define MUX_STAT_TOP_PERIC1 … #define DIV_TOP0 … #define DIV_TOP1 … #define DIV_TOP2 … #define DIV_TOP3 … #define DIV_TOP4 … #define DIV_TOP_MSCL … #define DIV_TOP_CAM10 … #define DIV_TOP_CAM11 … #define DIV_TOP_FSYS0 … #define DIV_TOP_FSYS1 … #define DIV_TOP_FSYS2 … #define DIV_TOP_PERIC0 … #define DIV_TOP_PERIC1 … #define DIV_TOP_PERIC2 … #define DIV_TOP_PERIC3 … #define DIV_TOP_PERIC4 … #define DIV_TOP_PLL_FREQ_DET … #define DIV_STAT_TOP0 … #define DIV_STAT_TOP1 … #define DIV_STAT_TOP2 … #define DIV_STAT_TOP3 … #define DIV_STAT_TOP4 … #define DIV_STAT_TOP_MSCL … #define DIV_STAT_TOP_CAM10 … #define DIV_STAT_TOP_CAM11 … #define DIV_STAT_TOP_FSYS0 … #define DIV_STAT_TOP_FSYS1 … #define DIV_STAT_TOP_FSYS2 … #define DIV_STAT_TOP_PERIC0 … #define DIV_STAT_TOP_PERIC1 … #define DIV_STAT_TOP_PERIC2 … #define DIV_STAT_TOP_PERIC3 … #define DIV_STAT_TOP_PLL_FREQ_DET … #define ENABLE_ACLK_TOP … #define ENABLE_SCLK_TOP … #define ENABLE_SCLK_TOP_MSCL … #define ENABLE_SCLK_TOP_CAM1 … #define ENABLE_SCLK_TOP_DISP … #define ENABLE_SCLK_TOP_FSYS … #define ENABLE_SCLK_TOP_PERIC … #define ENABLE_IP_TOP … #define ENABLE_CMU_TOP … #define ENABLE_CMU_TOP_DIV_STAT … static const unsigned long top_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump top_suspend_regs[] = …; /* list of all parent clock list */ PNAME(mout_aud_pll_p) = …; PNAME(mout_isp_pll_p) = …; PNAME(mout_aud_pll_user_p) = …; PNAME(mout_mphy_pll_user_p) = …; PNAME(mout_mfc_pll_user_p) = …; PNAME(mout_bus_pll_user_p) = …; PNAME(mout_bus_pll_user_t_p) = …; PNAME(mout_mphy_pll_user_t_p) = …; PNAME(mout_bus_mfc_pll_user_p) = …; PNAME(mout_mfc_bus_pll_user_p) = …; PNAME(mout_aclk_cam1_552_b_p) = …; PNAME(mout_aclk_cam1_552_a_p) = …; PNAME(mout_aclk_mfc_400_c_p) = …; PNAME(mout_aclk_mfc_400_b_p) = …; PNAME(mout_aclk_mfc_400_a_p) = …; PNAME(mout_bus_mphy_pll_user_p) = …; PNAME(mout_aclk_mscl_b_p) = …; PNAME(mout_aclk_g2d_400_b_p) = …; PNAME(mout_sclk_jpeg_c_p) = …; PNAME(mout_sclk_jpeg_b_p) = …; PNAME(mout_sclk_mmc2_b_p) = …; PNAME(mout_sclk_mmc1_b_p) = …; PNAME(mout_sclk_mmc0_d_p) = …; PNAME(mout_sclk_mmc0_c_p) = …; PNAME(mout_sclk_mmc0_b_p) = …; PNAME(mout_sclk_spdif_p) = …; PNAME(mout_sclk_audio1_p) = …; PNAME(mout_sclk_audio0_p) = …; PNAME(mout_sclk_hdmi_spdif_p) = …; static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = …; static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = …; static const struct samsung_mux_clock top_mux_clks[] __initconst = …; static const struct samsung_div_clock top_div_clks[] __initconst = …; static const struct samsung_gate_clock top_gate_clks[] __initconst = …; /* * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL */ static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = …; /* AUD_PLL */ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = …; static const struct samsung_pll_clock top_pll_clks[] __initconst = …; static const struct samsung_cmu_info top_cmu_info __initconst = …; static void __init exynos5433_cmu_top_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", exynos5433_cmu_top_init); /* * Register offset definitions for CMU_CPIF */ #define MPHY_PLL_LOCK … #define MPHY_PLL_CON0 … #define MPHY_PLL_CON1 … #define MPHY_PLL_FREQ_DET … #define MUX_SEL_CPIF0 … #define DIV_CPIF … #define ENABLE_SCLK_CPIF … static const unsigned long cpif_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump cpif_suspend_regs[] = …; /* list of all parent clock list */ PNAME(mout_mphy_pll_p) = …; static const struct samsung_pll_clock cpif_pll_clks[] __initconst = …; static const struct samsung_mux_clock cpif_mux_clks[] __initconst = …; static const struct samsung_div_clock cpif_div_clks[] __initconst = …; static const struct samsung_gate_clock cpif_gate_clks[] __initconst = …; static const struct samsung_cmu_info cpif_cmu_info __initconst = …; static void __init exynos5433_cmu_cpif_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", exynos5433_cmu_cpif_init); /* * Register offset definitions for CMU_MIF */ #define MEM0_PLL_LOCK … #define MEM1_PLL_LOCK … #define BUS_PLL_LOCK … #define MFC_PLL_LOCK … #define MEM0_PLL_CON0 … #define MEM0_PLL_CON1 … #define MEM0_PLL_FREQ_DET … #define MEM1_PLL_CON0 … #define MEM1_PLL_CON1 … #define MEM1_PLL_FREQ_DET … #define BUS_PLL_CON0 … #define BUS_PLL_CON1 … #define BUS_PLL_FREQ_DET … #define MFC_PLL_CON0 … #define MFC_PLL_CON1 … #define MFC_PLL_FREQ_DET … #define MUX_SEL_MIF0 … #define MUX_SEL_MIF1 … #define MUX_SEL_MIF2 … #define MUX_SEL_MIF3 … #define MUX_SEL_MIF4 … #define MUX_SEL_MIF5 … #define MUX_SEL_MIF6 … #define MUX_SEL_MIF7 … #define MUX_ENABLE_MIF0 … #define MUX_ENABLE_MIF1 … #define MUX_ENABLE_MIF2 … #define MUX_ENABLE_MIF3 … #define MUX_ENABLE_MIF4 … #define MUX_ENABLE_MIF5 … #define MUX_ENABLE_MIF6 … #define MUX_ENABLE_MIF7 … #define MUX_STAT_MIF0 … #define MUX_STAT_MIF1 … #define MUX_STAT_MIF2 … #define MUX_STAT_MIF3 … #define MUX_STAT_MIF4 … #define MUX_STAT_MIF5 … #define MUX_STAT_MIF6 … #define MUX_STAT_MIF7 … #define DIV_MIF1 … #define DIV_MIF2 … #define DIV_MIF3 … #define DIV_MIF4 … #define DIV_MIF5 … #define DIV_MIF_PLL_FREQ_DET … #define DIV_STAT_MIF1 … #define DIV_STAT_MIF2 … #define DIV_STAT_MIF3 … #define DIV_STAT_MIF4 … #define DIV_STAT_MIF5 … #define DIV_STAT_MIF_PLL_FREQ_DET … #define ENABLE_ACLK_MIF0 … #define ENABLE_ACLK_MIF1 … #define ENABLE_ACLK_MIF2 … #define ENABLE_ACLK_MIF3 … #define ENABLE_PCLK_MIF … #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ … #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ … #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT … #define ENABLE_PCLK_MIF_SECURE_RTC … #define ENABLE_SCLK_MIF … #define ENABLE_IP_MIF0 … #define ENABLE_IP_MIF1 … #define ENABLE_IP_MIF2 … #define ENABLE_IP_MIF3 … #define ENABLE_IP_MIF_SECURE_DREX0_TZ … #define ENABLE_IP_MIF_SECURE_DREX1_TZ … #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT … #define ENABLE_IP_MIF_SECURE_RTC … #define CLKOUT_CMU_MIF … #define CLKOUT_CMU_MIF_DIV_STAT … #define DREX_FREQ_CTRL0 … #define DREX_FREQ_CTRL1 … #define PAUSE … #define DDRPHY_LOCK_CTRL … static const unsigned long mif_clk_regs[] __initconst = …; static const struct samsung_pll_clock mif_pll_clks[] __initconst = …; /* list of all parent clock list */ PNAME(mout_mfc_pll_div2_p) = …; PNAME(mout_bus_pll_div2_p) = …; PNAME(mout_mem1_pll_div2_p) = …; PNAME(mout_mem0_pll_div2_p) = …; PNAME(mout_mfc_pll_p) = …; PNAME(mout_bus_pll_p) = …; PNAME(mout_mem1_pll_p) = …; PNAME(mout_mem0_pll_p) = …; PNAME(mout_clk2x_phy_c_p) = …; PNAME(mout_clk2x_phy_b_p) = …; PNAME(mout_clk2x_phy_a_p) = …; PNAME(mout_clkm_phy_b_p) = …; PNAME(mout_aclk_mifnm_200_p) = …; PNAME(mout_aclk_mifnm_400_p) = …; PNAME(mout_aclk_disp_333_b_p) = …; PNAME(mout_aclk_disp_333_a_p) = …; PNAME(mout_sclk_decon_vclk_c_p) = …; PNAME(mout_sclk_decon_vclk_b_p) = …; PNAME(mout_sclk_decon_p) = …; PNAME(mout_sclk_decon_eclk_c_p) = …; PNAME(mout_sclk_decon_eclk_b_p) = …; PNAME(mout_sclk_decon_tv_eclk_c_p) = …; PNAME(mout_sclk_decon_tv_eclk_b_p) = …; PNAME(mout_sclk_dsd_c_p) = …; PNAME(mout_sclk_dsd_b_p) = …; PNAME(mout_sclk_dsd_a_p) = …; PNAME(mout_sclk_dsim0_c_p) = …; PNAME(mout_sclk_dsim0_b_p) = …; PNAME(mout_sclk_decon_tv_vclk_c_p) = …; PNAME(mout_sclk_decon_tv_vclk_b_p) = …; PNAME(mout_sclk_dsim1_c_p) = …; PNAME(mout_sclk_dsim1_b_p) = …; static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = …; static const struct samsung_mux_clock mif_mux_clks[] __initconst = …; static const struct samsung_div_clock mif_div_clks[] __initconst = …; static const struct samsung_gate_clock mif_gate_clks[] __initconst = …; static const struct samsung_cmu_info mif_cmu_info __initconst = …; static void __init exynos5433_cmu_mif_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", exynos5433_cmu_mif_init); /* * Register offset definitions for CMU_PERIC */ #define DIV_PERIC … #define DIV_STAT_PERIC … #define ENABLE_ACLK_PERIC … #define ENABLE_PCLK_PERIC0 … #define ENABLE_PCLK_PERIC1 … #define ENABLE_SCLK_PERIC … #define ENABLE_IP_PERIC0 … #define ENABLE_IP_PERIC1 … #define ENABLE_IP_PERIC2 … static const unsigned long peric_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump peric_suspend_regs[] = …; static const struct samsung_div_clock peric_div_clks[] __initconst = …; static const struct samsung_gate_clock peric_gate_clks[] __initconst = …; static const struct samsung_cmu_info peric_cmu_info __initconst = …; static void __init exynos5433_cmu_peric_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", exynos5433_cmu_peric_init); /* * Register offset definitions for CMU_PERIS */ #define ENABLE_ACLK_PERIS … #define ENABLE_PCLK_PERIS … #define ENABLE_PCLK_PERIS_SECURE_TZPC … #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF … #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF … #define ENABLE_PCLK_PERIS_SECURE_TOPRTC … #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF … #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF … #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF … #define ENABLE_SCLK_PERIS … #define ENABLE_SCLK_PERIS_SECURE_SECKEY … #define ENABLE_SCLK_PERIS_SECURE_CHIPID … #define ENABLE_SCLK_PERIS_SECURE_TOPRTC … #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE … #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT … #define ENABLE_SCLK_PERIS_SECURE_OTP_CON … #define ENABLE_IP_PERIS0 … #define ENABLE_IP_PERIS1 … #define ENABLE_IP_PERIS_SECURE_TZPC … #define ENABLE_IP_PERIS_SECURE_SECKEY … #define ENABLE_IP_PERIS_SECURE_CHIPID … #define ENABLE_IP_PERIS_SECURE_TOPRTC … #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE … #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT … #define ENABLE_IP_PERIS_SECURE_OTP_CON … static const unsigned long peris_clk_regs[] __initconst = …; static const struct samsung_gate_clock peris_gate_clks[] __initconst = …; static const struct samsung_cmu_info peris_cmu_info __initconst = …; static void __init exynos5433_cmu_peris_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", exynos5433_cmu_peris_init); /* * Register offset definitions for CMU_FSYS */ #define MUX_SEL_FSYS0 … #define MUX_SEL_FSYS1 … #define MUX_SEL_FSYS2 … #define MUX_SEL_FSYS3 … #define MUX_SEL_FSYS4 … #define MUX_ENABLE_FSYS0 … #define MUX_ENABLE_FSYS1 … #define MUX_ENABLE_FSYS2 … #define MUX_ENABLE_FSYS3 … #define MUX_ENABLE_FSYS4 … #define MUX_STAT_FSYS0 … #define MUX_STAT_FSYS1 … #define MUX_STAT_FSYS2 … #define MUX_STAT_FSYS3 … #define MUX_STAT_FSYS4 … #define MUX_IGNORE_FSYS2 … #define MUX_IGNORE_FSYS3 … #define ENABLE_ACLK_FSYS0 … #define ENABLE_ACLK_FSYS1 … #define ENABLE_PCLK_FSYS … #define ENABLE_SCLK_FSYS … #define ENABLE_IP_FSYS0 … #define ENABLE_IP_FSYS1 … /* list of all parent clock list */ PNAME(mout_sclk_ufs_mphy_user_p) = …; PNAME(mout_aclk_fsys_200_user_p) = …; PNAME(mout_sclk_pcie_100_user_p) = …; PNAME(mout_sclk_ufsunipro_user_p) = …; PNAME(mout_sclk_mmc2_user_p) = …; PNAME(mout_sclk_mmc1_user_p) = …; PNAME(mout_sclk_mmc0_user_p) = …; PNAME(mout_sclk_usbhost30_user_p) = …; PNAME(mout_sclk_usbdrd30_user_p) = …; PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) = …; PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p) = …; PNAME(mout_phyclk_usbhost20_phy_hsic1_p) = …; PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p) = …; PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p) = …; PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p) = …; PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) = …; PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p) = …; PNAME(mout_phyclk_ufs_rx1_symbol_user_p) = …; PNAME(mout_phyclk_ufs_rx0_symbol_user_p) = …; PNAME(mout_phyclk_ufs_tx1_symbol_user_p) = …; PNAME(mout_phyclk_ufs_tx0_symbol_user_p) = …; PNAME(mout_phyclk_lli_mphy_to_ufs_user_p) = …; PNAME(mout_sclk_mphy_p) = …; static const unsigned long fsys_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump fsys_suspend_regs[] = …; static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = …; static const struct samsung_mux_clock fsys_mux_clks[] __initconst = …; static const struct samsung_gate_clock fsys_gate_clks[] __initconst = …; static const struct samsung_cmu_info fsys_cmu_info __initconst = …; /* * Register offset definitions for CMU_G2D */ #define MUX_SEL_G2D0 … #define MUX_SEL_ENABLE_G2D0 … #define MUX_SEL_STAT_G2D0 … #define DIV_G2D … #define DIV_STAT_G2D … #define DIV_ENABLE_ACLK_G2D … #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D … #define DIV_ENABLE_PCLK_G2D … #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D … #define DIV_ENABLE_IP_G2D0 … #define DIV_ENABLE_IP_G2D1 … #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D … static const unsigned long g2d_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump g2d_suspend_regs[] = …; /* list of all parent clock list */ PNAME(mout_aclk_g2d_266_user_p) = …; PNAME(mout_aclk_g2d_400_user_p) = …; static const struct samsung_mux_clock g2d_mux_clks[] __initconst = …; static const struct samsung_div_clock g2d_div_clks[] __initconst = …; static const struct samsung_gate_clock g2d_gate_clks[] __initconst = …; static const struct samsung_cmu_info g2d_cmu_info __initconst = …; /* * Register offset definitions for CMU_DISP */ #define DISP_PLL_LOCK … #define DISP_PLL_CON0 … #define DISP_PLL_CON1 … #define DISP_PLL_FREQ_DET … #define MUX_SEL_DISP0 … #define MUX_SEL_DISP1 … #define MUX_SEL_DISP2 … #define MUX_SEL_DISP3 … #define MUX_SEL_DISP4 … #define MUX_ENABLE_DISP0 … #define MUX_ENABLE_DISP1 … #define MUX_ENABLE_DISP2 … #define MUX_ENABLE_DISP3 … #define MUX_ENABLE_DISP4 … #define MUX_STAT_DISP0 … #define MUX_STAT_DISP1 … #define MUX_STAT_DISP2 … #define MUX_STAT_DISP3 … #define MUX_STAT_DISP4 … #define MUX_IGNORE_DISP2 … #define DIV_DISP … #define DIV_DISP_PLL_FREQ_DET … #define DIV_STAT_DISP … #define DIV_STAT_DISP_PLL_FREQ_DET … #define ENABLE_ACLK_DISP0 … #define ENABLE_ACLK_DISP1 … #define ENABLE_PCLK_DISP … #define ENABLE_SCLK_DISP … #define ENABLE_IP_DISP0 … #define ENABLE_IP_DISP1 … #define CLKOUT_CMU_DISP … #define CLKOUT_CMU_DISP_DIV_STAT … static const unsigned long disp_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump disp_suspend_regs[] = …; /* list of all parent clock list */ PNAME(mout_disp_pll_p) = …; PNAME(mout_sclk_dsim1_user_p) = …; PNAME(mout_sclk_dsim0_user_p) = …; PNAME(mout_sclk_dsd_user_p) = …; PNAME(mout_sclk_decon_tv_eclk_user_p) = …; PNAME(mout_sclk_decon_vclk_user_p) = …; PNAME(mout_sclk_decon_eclk_user_p) = …; PNAME(mout_sclk_decon_tv_vlkc_user_p) = …; PNAME(mout_aclk_disp_333_user_p) = …; PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = …; PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = …; PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = …; PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = …; PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = …; PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = …; PNAME(mout_sclk_dsim0_p) = …; PNAME(mout_sclk_decon_tv_eclk_p) = …; PNAME(mout_sclk_decon_vclk_p) = …; PNAME(mout_sclk_decon_eclk_p) = …; PNAME(mout_sclk_dsim1_b_disp_p) = …; PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = …; PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = …; static const struct samsung_pll_clock disp_pll_clks[] __initconst = …; static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = …; static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = …; static const struct samsung_mux_clock disp_mux_clks[] __initconst = …; static const struct samsung_div_clock disp_div_clks[] __initconst = …; static const struct samsung_gate_clock disp_gate_clks[] __initconst = …; static const struct samsung_cmu_info disp_cmu_info __initconst = …; /* * Register offset definitions for CMU_AUD */ #define MUX_SEL_AUD0 … #define MUX_SEL_AUD1 … #define MUX_ENABLE_AUD0 … #define MUX_ENABLE_AUD1 … #define MUX_STAT_AUD0 … #define DIV_AUD0 … #define DIV_AUD1 … #define DIV_STAT_AUD0 … #define DIV_STAT_AUD1 … #define ENABLE_ACLK_AUD … #define ENABLE_PCLK_AUD … #define ENABLE_SCLK_AUD0 … #define ENABLE_SCLK_AUD1 … #define ENABLE_IP_AUD0 … #define ENABLE_IP_AUD1 … static const unsigned long aud_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump aud_suspend_regs[] = …; /* list of all parent clock list */ PNAME(mout_aud_pll_user_aud_p) = …; PNAME(mout_sclk_aud_pcm_p) = …; static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = …; static const struct samsung_mux_clock aud_mux_clks[] __initconst = …; static const struct samsung_div_clock aud_div_clks[] __initconst = …; static const struct samsung_gate_clock aud_gate_clks[] __initconst = …; static const struct samsung_cmu_info aud_cmu_info __initconst = …; /* * Register offset definitions for CMU_BUS{0|1|2} */ #define DIV_BUS … #define DIV_STAT_BUS … #define ENABLE_ACLK_BUS … #define ENABLE_PCLK_BUS … #define ENABLE_IP_BUS0 … #define ENABLE_IP_BUS1 … #define MUX_SEL_BUS2 … #define MUX_ENABLE_BUS2 … #define MUX_STAT_BUS2 … /* list of all parent clock list */ PNAME(mout_aclk_bus2_400_p) = …; #define CMU_BUS_COMMON_CLK_REGS … static const unsigned long bus01_clk_regs[] __initconst = …; static const unsigned long bus2_clk_regs[] __initconst = …; static const struct samsung_div_clock bus0_div_clks[] __initconst = …; /* CMU_BUS0 clocks */ static const struct samsung_gate_clock bus0_gate_clks[] __initconst = …; /* CMU_BUS1 clocks */ static const struct samsung_div_clock bus1_div_clks[] __initconst = …; static const struct samsung_gate_clock bus1_gate_clks[] __initconst = …; /* CMU_BUS2 clocks */ static const struct samsung_mux_clock bus2_mux_clks[] __initconst = …; static const struct samsung_div_clock bus2_div_clks[] __initconst = …; static const struct samsung_gate_clock bus2_gate_clks[] __initconst = …; #define CMU_BUS_INFO_CLKS(id) … static const struct samsung_cmu_info bus0_cmu_info __initconst = …; static const struct samsung_cmu_info bus1_cmu_info __initconst = …; static const struct samsung_cmu_info bus2_cmu_info __initconst = …; #define exynos5433_cmu_bus_init(id) … exynos5433_cmu_bus_init(…); exynos5433_cmu_bus_init(…); exynos5433_cmu_bus_init(…); /* * Register offset definitions for CMU_G3D */ #define G3D_PLL_LOCK … #define G3D_PLL_CON0 … #define G3D_PLL_CON1 … #define G3D_PLL_FREQ_DET … #define MUX_SEL_G3D … #define MUX_ENABLE_G3D … #define MUX_STAT_G3D … #define DIV_G3D … #define DIV_G3D_PLL_FREQ_DET … #define DIV_STAT_G3D … #define DIV_STAT_G3D_PLL_FREQ_DET … #define ENABLE_ACLK_G3D … #define ENABLE_PCLK_G3D … #define ENABLE_SCLK_G3D … #define ENABLE_IP_G3D0 … #define ENABLE_IP_G3D1 … #define CLKOUT_CMU_G3D … #define CLKOUT_CMU_G3D_DIV_STAT … #define CLK_STOPCTRL … static const unsigned long g3d_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump g3d_suspend_regs[] = …; /* list of all parent clock list */ PNAME(mout_aclk_g3d_400_p) = …; PNAME(mout_g3d_pll_p) = …; static const struct samsung_pll_clock g3d_pll_clks[] __initconst = …; static const struct samsung_mux_clock g3d_mux_clks[] __initconst = …; static const struct samsung_div_clock g3d_div_clks[] __initconst = …; static const struct samsung_gate_clock g3d_gate_clks[] __initconst = …; static const struct samsung_cmu_info g3d_cmu_info __initconst = …; /* * Register offset definitions for CMU_GSCL */ #define MUX_SEL_GSCL … #define MUX_ENABLE_GSCL … #define MUX_STAT_GSCL … #define ENABLE_ACLK_GSCL … #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 … #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 … #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 … #define ENABLE_PCLK_GSCL … #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 … #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 … #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 … #define ENABLE_IP_GSCL0 … #define ENABLE_IP_GSCL1 … #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 … #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 … #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 … static const unsigned long gscl_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump gscl_suspend_regs[] = …; /* list of all parent clock list */ PNAME(aclk_gscl_111_user_p) = …; PNAME(aclk_gscl_333_user_p) = …; static const struct samsung_mux_clock gscl_mux_clks[] __initconst = …; static const struct samsung_gate_clock gscl_gate_clks[] __initconst = …; static const struct samsung_cmu_info gscl_cmu_info __initconst = …; /* * Register offset definitions for CMU_APOLLO */ #define APOLLO_PLL_LOCK … #define APOLLO_PLL_CON0 … #define APOLLO_PLL_CON1 … #define APOLLO_PLL_FREQ_DET … #define MUX_SEL_APOLLO0 … #define MUX_SEL_APOLLO1 … #define MUX_SEL_APOLLO2 … #define MUX_ENABLE_APOLLO0 … #define MUX_ENABLE_APOLLO1 … #define MUX_ENABLE_APOLLO2 … #define MUX_STAT_APOLLO0 … #define MUX_STAT_APOLLO1 … #define MUX_STAT_APOLLO2 … #define DIV_APOLLO0 … #define DIV_APOLLO1 … #define DIV_APOLLO_PLL_FREQ_DET … #define DIV_STAT_APOLLO0 … #define DIV_STAT_APOLLO1 … #define DIV_STAT_APOLLO_PLL_FREQ_DET … #define ENABLE_ACLK_APOLLO … #define ENABLE_PCLK_APOLLO … #define ENABLE_SCLK_APOLLO … #define ENABLE_IP_APOLLO0 … #define ENABLE_IP_APOLLO1 … #define CLKOUT_CMU_APOLLO … #define CLKOUT_CMU_APOLLO_DIV_STAT … #define ARMCLK_STOPCTRL … #define APOLLO_PWR_CTRL … #define APOLLO_PWR_CTRL2 … #define APOLLO_INTR_SPREAD_ENABLE … #define APOLLO_INTR_SPREAD_USE_STANDBYWFI … #define APOLLO_INTR_SPREAD_BLOCKING_DURATION … static const unsigned long apollo_clk_regs[] __initconst = …; /* list of all parent clock list */ PNAME(mout_apollo_pll_p) = …; PNAME(mout_bus_pll_apollo_user_p) = …; PNAME(mout_apollo_p) = …; static const struct samsung_pll_clock apollo_pll_clks[] __initconst = …; static const struct samsung_mux_clock apollo_mux_clks[] __initconst = …; static const struct samsung_div_clock apollo_div_clks[] __initconst = …; static const struct samsung_gate_clock apollo_gate_clks[] __initconst = …; #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) … #define E5433_APOLLO_DIV1(hpm, copy) … static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = …; static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = …; static const struct samsung_cmu_info apollo_cmu_info __initconst = …; static void __init exynos5433_cmu_apollo_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", exynos5433_cmu_apollo_init); /* * Register offset definitions for CMU_ATLAS */ #define ATLAS_PLL_LOCK … #define ATLAS_PLL_CON0 … #define ATLAS_PLL_CON1 … #define ATLAS_PLL_FREQ_DET … #define MUX_SEL_ATLAS0 … #define MUX_SEL_ATLAS1 … #define MUX_SEL_ATLAS2 … #define MUX_ENABLE_ATLAS0 … #define MUX_ENABLE_ATLAS1 … #define MUX_ENABLE_ATLAS2 … #define MUX_STAT_ATLAS0 … #define MUX_STAT_ATLAS1 … #define MUX_STAT_ATLAS2 … #define DIV_ATLAS0 … #define DIV_ATLAS1 … #define DIV_ATLAS_PLL_FREQ_DET … #define DIV_STAT_ATLAS0 … #define DIV_STAT_ATLAS1 … #define DIV_STAT_ATLAS_PLL_FREQ_DET … #define ENABLE_ACLK_ATLAS … #define ENABLE_PCLK_ATLAS … #define ENABLE_SCLK_ATLAS … #define ENABLE_IP_ATLAS0 … #define ENABLE_IP_ATLAS1 … #define CLKOUT_CMU_ATLAS … #define CLKOUT_CMU_ATLAS_DIV_STAT … #define ARMCLK_STOPCTRL … #define ATLAS_PWR_CTRL … #define ATLAS_PWR_CTRL2 … #define ATLAS_INTR_SPREAD_ENABLE … #define ATLAS_INTR_SPREAD_USE_STANDBYWFI … #define ATLAS_INTR_SPREAD_BLOCKING_DURATION … static const unsigned long atlas_clk_regs[] __initconst = …; /* list of all parent clock list */ PNAME(mout_atlas_pll_p) = …; PNAME(mout_bus_pll_atlas_user_p) = …; PNAME(mout_atlas_p) = …; static const struct samsung_pll_clock atlas_pll_clks[] __initconst = …; static const struct samsung_mux_clock atlas_mux_clks[] __initconst = …; static const struct samsung_div_clock atlas_div_clks[] __initconst = …; static const struct samsung_gate_clock atlas_gate_clks[] __initconst = …; #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) … #define E5433_ATLAS_DIV1(hpm, copy) … static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = …; static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = …; static const struct samsung_cmu_info atlas_cmu_info __initconst = …; static void __init exynos5433_cmu_atlas_init(struct device_node *np) { … } CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", exynos5433_cmu_atlas_init); /* * Register offset definitions for CMU_MSCL */ #define MUX_SEL_MSCL0 … #define MUX_SEL_MSCL1 … #define MUX_ENABLE_MSCL0 … #define MUX_ENABLE_MSCL1 … #define MUX_STAT_MSCL0 … #define MUX_STAT_MSCL1 … #define DIV_MSCL … #define DIV_STAT_MSCL … #define ENABLE_ACLK_MSCL … #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 … #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 … #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG … #define ENABLE_PCLK_MSCL … #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 … #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 … #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG … #define ENABLE_SCLK_MSCL … #define ENABLE_IP_MSCL0 … #define ENABLE_IP_MSCL1 … #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 … #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 … #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG … static const unsigned long mscl_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump mscl_suspend_regs[] = …; /* list of all parent clock list */ PNAME(mout_sclk_jpeg_user_p) = …; PNAME(mout_aclk_mscl_400_user_p) = …; PNAME(mout_sclk_jpeg_p) = …; static const struct samsung_mux_clock mscl_mux_clks[] __initconst = …; static const struct samsung_div_clock mscl_div_clks[] __initconst = …; static const struct samsung_gate_clock mscl_gate_clks[] __initconst = …; static const struct samsung_cmu_info mscl_cmu_info __initconst = …; /* * Register offset definitions for CMU_MFC */ #define MUX_SEL_MFC … #define MUX_ENABLE_MFC … #define MUX_STAT_MFC … #define DIV_MFC … #define DIV_STAT_MFC … #define ENABLE_ACLK_MFC … #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC … #define ENABLE_PCLK_MFC … #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC … #define ENABLE_IP_MFC0 … #define ENABLE_IP_MFC1 … #define ENABLE_IP_MFC_SECURE_SMMU_MFC … static const unsigned long mfc_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump mfc_suspend_regs[] = …; PNAME(mout_aclk_mfc_400_user_p) = …; static const struct samsung_mux_clock mfc_mux_clks[] __initconst = …; static const struct samsung_div_clock mfc_div_clks[] __initconst = …; static const struct samsung_gate_clock mfc_gate_clks[] __initconst = …; static const struct samsung_cmu_info mfc_cmu_info __initconst = …; /* * Register offset definitions for CMU_HEVC */ #define MUX_SEL_HEVC … #define MUX_ENABLE_HEVC … #define MUX_STAT_HEVC … #define DIV_HEVC … #define DIV_STAT_HEVC … #define ENABLE_ACLK_HEVC … #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC … #define ENABLE_PCLK_HEVC … #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC … #define ENABLE_IP_HEVC0 … #define ENABLE_IP_HEVC1 … #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC … static const unsigned long hevc_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump hevc_suspend_regs[] = …; PNAME(mout_aclk_hevc_400_user_p) = …; static const struct samsung_mux_clock hevc_mux_clks[] __initconst = …; static const struct samsung_div_clock hevc_div_clks[] __initconst = …; static const struct samsung_gate_clock hevc_gate_clks[] __initconst = …; static const struct samsung_cmu_info hevc_cmu_info __initconst = …; /* * Register offset definitions for CMU_ISP */ #define MUX_SEL_ISP … #define MUX_ENABLE_ISP … #define MUX_STAT_ISP … #define DIV_ISP … #define DIV_STAT_ISP … #define ENABLE_ACLK_ISP0 … #define ENABLE_ACLK_ISP1 … #define ENABLE_ACLK_ISP2 … #define ENABLE_PCLK_ISP … #define ENABLE_SCLK_ISP … #define ENABLE_IP_ISP0 … #define ENABLE_IP_ISP1 … #define ENABLE_IP_ISP2 … #define ENABLE_IP_ISP3 … static const unsigned long isp_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump isp_suspend_regs[] = …; PNAME(mout_aclk_isp_dis_400_user_p) = …; PNAME(mout_aclk_isp_400_user_p) = …; static const struct samsung_mux_clock isp_mux_clks[] __initconst = …; static const struct samsung_div_clock isp_div_clks[] __initconst = …; static const struct samsung_gate_clock isp_gate_clks[] __initconst = …; static const struct samsung_cmu_info isp_cmu_info __initconst = …; /* * Register offset definitions for CMU_CAM0 */ #define MUX_SEL_CAM00 … #define MUX_SEL_CAM01 … #define MUX_SEL_CAM02 … #define MUX_SEL_CAM03 … #define MUX_SEL_CAM04 … #define MUX_ENABLE_CAM00 … #define MUX_ENABLE_CAM01 … #define MUX_ENABLE_CAM02 … #define MUX_ENABLE_CAM03 … #define MUX_ENABLE_CAM04 … #define MUX_STAT_CAM00 … #define MUX_STAT_CAM01 … #define MUX_STAT_CAM02 … #define MUX_STAT_CAM03 … #define MUX_STAT_CAM04 … #define MUX_IGNORE_CAM01 … #define DIV_CAM00 … #define DIV_CAM01 … #define DIV_CAM02 … #define DIV_CAM03 … #define DIV_STAT_CAM00 … #define DIV_STAT_CAM01 … #define DIV_STAT_CAM02 … #define DIV_STAT_CAM03 … #define ENABLE_ACLK_CAM00 … #define ENABLE_ACLK_CAM01 … #define ENABLE_ACLK_CAM02 … #define ENABLE_PCLK_CAM0 … #define ENABLE_SCLK_CAM0 … #define ENABLE_IP_CAM00 … #define ENABLE_IP_CAM01 … #define ENABLE_IP_CAM02 … #define ENABLE_IP_CAM03 … static const unsigned long cam0_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump cam0_suspend_regs[] = …; PNAME(mout_aclk_cam0_333_user_p) = …; PNAME(mout_aclk_cam0_400_user_p) = …; PNAME(mout_aclk_cam0_552_user_p) = …; PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = …; PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = …; PNAME(mout_aclk_lite_d_b_p) = …; PNAME(mout_aclk_lite_d_a_p) = …; PNAME(mout_aclk_lite_b_b_p) = …; PNAME(mout_aclk_lite_b_a_p) = …; PNAME(mout_aclk_lite_a_b_p) = …; PNAME(mout_aclk_lite_a_a_p) = …; PNAME(mout_aclk_cam0_400_p) = …; PNAME(mout_aclk_csis1_b_p) = …; PNAME(mout_aclk_csis1_a_p) = …; PNAME(mout_aclk_csis0_b_p) = …; PNAME(mout_aclk_csis0_a_p) = …; PNAME(mout_aclk_3aa1_b_p) = …; PNAME(mout_aclk_3aa1_a_p) = …; PNAME(mout_aclk_3aa0_b_p) = …; PNAME(mout_aclk_3aa0_a_p) = …; PNAME(mout_sclk_lite_freecnt_c_p) = …; PNAME(mout_sclk_lite_freecnt_b_p) = …; PNAME(mout_sclk_lite_freecnt_a_p) = …; PNAME(mout_sclk_pixelasync_lite_c_b_p) = …; PNAME(mout_sclk_pixelasync_lite_c_a_p) = …; PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = …; PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = …; static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = …; static const struct samsung_mux_clock cam0_mux_clks[] __initconst = …; static const struct samsung_div_clock cam0_div_clks[] __initconst = …; static const struct samsung_gate_clock cam0_gate_clks[] __initconst = …; static const struct samsung_cmu_info cam0_cmu_info __initconst = …; /* * Register offset definitions for CMU_CAM1 */ #define MUX_SEL_CAM10 … #define MUX_SEL_CAM11 … #define MUX_SEL_CAM12 … #define MUX_ENABLE_CAM10 … #define MUX_ENABLE_CAM11 … #define MUX_ENABLE_CAM12 … #define MUX_STAT_CAM10 … #define MUX_STAT_CAM11 … #define MUX_STAT_CAM12 … #define MUX_IGNORE_CAM11 … #define DIV_CAM10 … #define DIV_CAM11 … #define DIV_STAT_CAM10 … #define DIV_STAT_CAM11 … #define ENABLE_ACLK_CAM10 … #define ENABLE_ACLK_CAM11 … #define ENABLE_ACLK_CAM12 … #define ENABLE_PCLK_CAM1 … #define ENABLE_SCLK_CAM1 … #define ENABLE_IP_CAM10 … #define ENABLE_IP_CAM11 … #define ENABLE_IP_CAM12 … static const unsigned long cam1_clk_regs[] __initconst = …; static const struct samsung_clk_reg_dump cam1_suspend_regs[] = …; PNAME(mout_sclk_isp_uart_user_p) = …; PNAME(mout_sclk_isp_spi1_user_p) = …; PNAME(mout_sclk_isp_spi0_user_p) = …; PNAME(mout_aclk_cam1_333_user_p) = …; PNAME(mout_aclk_cam1_400_user_p) = …; PNAME(mout_aclk_cam1_552_user_p) = …; PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = …; PNAME(mout_aclk_csis2_b_p) = …; PNAME(mout_aclk_csis2_a_p) = …; PNAME(mout_aclk_fd_b_p) = …; PNAME(mout_aclk_fd_a_p) = …; PNAME(mout_aclk_lite_c_b_p) = …; PNAME(mout_aclk_lite_c_a_p) = …; static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = …; static const struct samsung_mux_clock cam1_mux_clks[] __initconst = …; static const struct samsung_div_clock cam1_div_clks[] __initconst = …; static const struct samsung_gate_clock cam1_gate_clks[] __initconst = …; static const struct samsung_cmu_info cam1_cmu_info __initconst = …; /* * Register offset definitions for CMU_IMEM */ #define ENABLE_ACLK_IMEM_SLIMSSS … #define ENABLE_PCLK_IMEM_SLIMSSS … static const unsigned long imem_clk_regs[] __initconst = …; static const struct samsung_gate_clock imem_gate_clks[] __initconst = …; static const struct samsung_cmu_info imem_cmu_info __initconst = …; static int __init exynos5433_cmu_probe(struct platform_device *pdev) { … } static const struct of_device_id exynos5433_cmu_of_match[] = …; static const struct dev_pm_ops exynos5433_cmu_pm_ops = …; static struct platform_driver exynos5433_cmu_driver __refdata = …; static int __init exynos5433_cmu_init(void) { … } core_initcall(exynos5433_cmu_init);
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