/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright 2022 Emil Renner Berthing <[email protected]> * Copyright 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ /* PLL clocks */ #define JH7110_PLLCLK_PLL0_OUT … #define JH7110_PLLCLK_PLL1_OUT … #define JH7110_PLLCLK_PLL2_OUT … #define JH7110_PLLCLK_END … /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT … #define JH7110_SYSCLK_CPU_CORE … #define JH7110_SYSCLK_CPU_BUS … #define JH7110_SYSCLK_GPU_ROOT … #define JH7110_SYSCLK_PERH_ROOT … #define JH7110_SYSCLK_BUS_ROOT … #define JH7110_SYSCLK_NOCSTG_BUS … #define JH7110_SYSCLK_AXI_CFG0 … #define JH7110_SYSCLK_STG_AXIAHB … #define JH7110_SYSCLK_AHB0 … #define JH7110_SYSCLK_AHB1 … #define JH7110_SYSCLK_APB_BUS … #define JH7110_SYSCLK_APB0 … #define JH7110_SYSCLK_PLL0_DIV2 … #define JH7110_SYSCLK_PLL1_DIV2 … #define JH7110_SYSCLK_PLL2_DIV2 … #define JH7110_SYSCLK_AUDIO_ROOT … #define JH7110_SYSCLK_MCLK_INNER … #define JH7110_SYSCLK_MCLK … #define JH7110_SYSCLK_MCLK_OUT … #define JH7110_SYSCLK_ISP_2X … #define JH7110_SYSCLK_ISP_AXI … #define JH7110_SYSCLK_GCLK0 … #define JH7110_SYSCLK_GCLK1 … #define JH7110_SYSCLK_GCLK2 … #define JH7110_SYSCLK_CORE … #define JH7110_SYSCLK_CORE1 … #define JH7110_SYSCLK_CORE2 … #define JH7110_SYSCLK_CORE3 … #define JH7110_SYSCLK_CORE4 … #define JH7110_SYSCLK_DEBUG … #define JH7110_SYSCLK_RTC_TOGGLE … #define JH7110_SYSCLK_TRACE0 … #define JH7110_SYSCLK_TRACE1 … #define JH7110_SYSCLK_TRACE2 … #define JH7110_SYSCLK_TRACE3 … #define JH7110_SYSCLK_TRACE4 … #define JH7110_SYSCLK_TRACE_COM … #define JH7110_SYSCLK_NOC_BUS_CPU_AXI … #define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI … #define JH7110_SYSCLK_OSC_DIV2 … #define JH7110_SYSCLK_PLL1_DIV4 … #define JH7110_SYSCLK_PLL1_DIV8 … #define JH7110_SYSCLK_DDR_BUS … #define JH7110_SYSCLK_DDR_AXI … #define JH7110_SYSCLK_GPU_CORE … #define JH7110_SYSCLK_GPU_CORE_CLK … #define JH7110_SYSCLK_GPU_SYS_CLK … #define JH7110_SYSCLK_GPU_APB … #define JH7110_SYSCLK_GPU_RTC_TOGGLE … #define JH7110_SYSCLK_NOC_BUS_GPU_AXI … #define JH7110_SYSCLK_ISP_TOP_CORE … #define JH7110_SYSCLK_ISP_TOP_AXI … #define JH7110_SYSCLK_NOC_BUS_ISP_AXI … #define JH7110_SYSCLK_HIFI4_CORE … #define JH7110_SYSCLK_HIFI4_AXI … #define JH7110_SYSCLK_AXI_CFG1_MAIN … #define JH7110_SYSCLK_AXI_CFG1_AHB … #define JH7110_SYSCLK_VOUT_SRC … #define JH7110_SYSCLK_VOUT_AXI … #define JH7110_SYSCLK_NOC_BUS_DISP_AXI … #define JH7110_SYSCLK_VOUT_TOP_AHB … #define JH7110_SYSCLK_VOUT_TOP_AXI … #define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK … #define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF … #define JH7110_SYSCLK_JPEGC_AXI … #define JH7110_SYSCLK_CODAJ12_AXI … #define JH7110_SYSCLK_CODAJ12_CORE … #define JH7110_SYSCLK_CODAJ12_APB … #define JH7110_SYSCLK_VDEC_AXI … #define JH7110_SYSCLK_WAVE511_AXI … #define JH7110_SYSCLK_WAVE511_BPU … #define JH7110_SYSCLK_WAVE511_VCE … #define JH7110_SYSCLK_WAVE511_APB … #define JH7110_SYSCLK_VDEC_JPG … #define JH7110_SYSCLK_VDEC_MAIN … #define JH7110_SYSCLK_NOC_BUS_VDEC_AXI … #define JH7110_SYSCLK_VENC_AXI … #define JH7110_SYSCLK_WAVE420L_AXI … #define JH7110_SYSCLK_WAVE420L_BPU … #define JH7110_SYSCLK_WAVE420L_VCE … #define JH7110_SYSCLK_WAVE420L_APB … #define JH7110_SYSCLK_NOC_BUS_VENC_AXI … #define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV … #define JH7110_SYSCLK_AXI_CFG0_MAIN … #define JH7110_SYSCLK_AXI_CFG0_HIFI4 … #define JH7110_SYSCLK_AXIMEM2_AXI … #define JH7110_SYSCLK_QSPI_AHB … #define JH7110_SYSCLK_QSPI_APB … #define JH7110_SYSCLK_QSPI_REF_SRC … #define JH7110_SYSCLK_QSPI_REF … #define JH7110_SYSCLK_SDIO0_AHB … #define JH7110_SYSCLK_SDIO1_AHB … #define JH7110_SYSCLK_SDIO0_SDCARD … #define JH7110_SYSCLK_SDIO1_SDCARD … #define JH7110_SYSCLK_USB_125M … #define JH7110_SYSCLK_NOC_BUS_STG_AXI … #define JH7110_SYSCLK_GMAC1_AHB … #define JH7110_SYSCLK_GMAC1_AXI … #define JH7110_SYSCLK_GMAC_SRC … #define JH7110_SYSCLK_GMAC1_GTXCLK … #define JH7110_SYSCLK_GMAC1_RMII_RTX … #define JH7110_SYSCLK_GMAC1_PTP … #define JH7110_SYSCLK_GMAC1_RX … #define JH7110_SYSCLK_GMAC1_RX_INV … #define JH7110_SYSCLK_GMAC1_TX … #define JH7110_SYSCLK_GMAC1_TX_INV … #define JH7110_SYSCLK_GMAC1_GTXC … #define JH7110_SYSCLK_GMAC0_GTXCLK … #define JH7110_SYSCLK_GMAC0_PTP … #define JH7110_SYSCLK_GMAC_PHY … #define JH7110_SYSCLK_GMAC0_GTXC … #define JH7110_SYSCLK_IOMUX_APB … #define JH7110_SYSCLK_MAILBOX_APB … #define JH7110_SYSCLK_INT_CTRL_APB … #define JH7110_SYSCLK_CAN0_APB … #define JH7110_SYSCLK_CAN0_TIMER … #define JH7110_SYSCLK_CAN0_CAN … #define JH7110_SYSCLK_CAN1_APB … #define JH7110_SYSCLK_CAN1_TIMER … #define JH7110_SYSCLK_CAN1_CAN … #define JH7110_SYSCLK_PWM_APB … #define JH7110_SYSCLK_WDT_APB … #define JH7110_SYSCLK_WDT_CORE … #define JH7110_SYSCLK_TIMER_APB … #define JH7110_SYSCLK_TIMER0 … #define JH7110_SYSCLK_TIMER1 … #define JH7110_SYSCLK_TIMER2 … #define JH7110_SYSCLK_TIMER3 … #define JH7110_SYSCLK_TEMP_APB … #define JH7110_SYSCLK_TEMP_CORE … #define JH7110_SYSCLK_SPI0_APB … #define JH7110_SYSCLK_SPI1_APB … #define JH7110_SYSCLK_SPI2_APB … #define JH7110_SYSCLK_SPI3_APB … #define JH7110_SYSCLK_SPI4_APB … #define JH7110_SYSCLK_SPI5_APB … #define JH7110_SYSCLK_SPI6_APB … #define JH7110_SYSCLK_I2C0_APB … #define JH7110_SYSCLK_I2C1_APB … #define JH7110_SYSCLK_I2C2_APB … #define JH7110_SYSCLK_I2C3_APB … #define JH7110_SYSCLK_I2C4_APB … #define JH7110_SYSCLK_I2C5_APB … #define JH7110_SYSCLK_I2C6_APB … #define JH7110_SYSCLK_UART0_APB … #define JH7110_SYSCLK_UART0_CORE … #define JH7110_SYSCLK_UART1_APB … #define JH7110_SYSCLK_UART1_CORE … #define JH7110_SYSCLK_UART2_APB … #define JH7110_SYSCLK_UART2_CORE … #define JH7110_SYSCLK_UART3_APB … #define JH7110_SYSCLK_UART3_CORE … #define JH7110_SYSCLK_UART4_APB … #define JH7110_SYSCLK_UART4_CORE … #define JH7110_SYSCLK_UART5_APB … #define JH7110_SYSCLK_UART5_CORE … #define JH7110_SYSCLK_PWMDAC_APB … #define JH7110_SYSCLK_PWMDAC_CORE … #define JH7110_SYSCLK_SPDIF_APB … #define JH7110_SYSCLK_SPDIF_CORE … #define JH7110_SYSCLK_I2STX0_APB … #define JH7110_SYSCLK_I2STX0_BCLK_MST … #define JH7110_SYSCLK_I2STX0_BCLK_MST_INV … #define JH7110_SYSCLK_I2STX0_LRCK_MST … #define JH7110_SYSCLK_I2STX0_BCLK … #define JH7110_SYSCLK_I2STX0_BCLK_INV … #define JH7110_SYSCLK_I2STX0_LRCK … #define JH7110_SYSCLK_I2STX1_APB … #define JH7110_SYSCLK_I2STX1_BCLK_MST … #define JH7110_SYSCLK_I2STX1_BCLK_MST_INV … #define JH7110_SYSCLK_I2STX1_LRCK_MST … #define JH7110_SYSCLK_I2STX1_BCLK … #define JH7110_SYSCLK_I2STX1_BCLK_INV … #define JH7110_SYSCLK_I2STX1_LRCK … #define JH7110_SYSCLK_I2SRX_APB … #define JH7110_SYSCLK_I2SRX_BCLK_MST … #define JH7110_SYSCLK_I2SRX_BCLK_MST_INV … #define JH7110_SYSCLK_I2SRX_LRCK_MST … #define JH7110_SYSCLK_I2SRX_BCLK … #define JH7110_SYSCLK_I2SRX_BCLK_INV … #define JH7110_SYSCLK_I2SRX_LRCK … #define JH7110_SYSCLK_PDM_DMIC … #define JH7110_SYSCLK_PDM_APB … #define JH7110_SYSCLK_TDM_AHB … #define JH7110_SYSCLK_TDM_APB … #define JH7110_SYSCLK_TDM_INTERNAL … #define JH7110_SYSCLK_TDM_TDM … #define JH7110_SYSCLK_TDM_TDM_INV … #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG … #define JH7110_SYSCLK_END … /* AONCRG clocks */ #define JH7110_AONCLK_OSC_DIV4 … #define JH7110_AONCLK_APB_FUNC … #define JH7110_AONCLK_GMAC0_AHB … #define JH7110_AONCLK_GMAC0_AXI … #define JH7110_AONCLK_GMAC0_RMII_RTX … #define JH7110_AONCLK_GMAC0_TX … #define JH7110_AONCLK_GMAC0_TX_INV … #define JH7110_AONCLK_GMAC0_RX … #define JH7110_AONCLK_GMAC0_RX_INV … #define JH7110_AONCLK_OTPC_APB … #define JH7110_AONCLK_RTC_APB … #define JH7110_AONCLK_RTC_INTERNAL … #define JH7110_AONCLK_RTC_32K … #define JH7110_AONCLK_RTC_CAL … #define JH7110_AONCLK_END … /* STGCRG clocks */ #define JH7110_STGCLK_HIFI4_CLK_CORE … #define JH7110_STGCLK_USB0_APB … #define JH7110_STGCLK_USB0_UTMI_APB … #define JH7110_STGCLK_USB0_AXI … #define JH7110_STGCLK_USB0_LPM … #define JH7110_STGCLK_USB0_STB … #define JH7110_STGCLK_USB0_APP_125 … #define JH7110_STGCLK_USB0_REFCLK … #define JH7110_STGCLK_PCIE0_AXI_MST0 … #define JH7110_STGCLK_PCIE0_APB … #define JH7110_STGCLK_PCIE0_TL … #define JH7110_STGCLK_PCIE1_AXI_MST0 … #define JH7110_STGCLK_PCIE1_APB … #define JH7110_STGCLK_PCIE1_TL … #define JH7110_STGCLK_PCIE_SLV_MAIN … #define JH7110_STGCLK_SEC_AHB … #define JH7110_STGCLK_SEC_MISC_AHB … #define JH7110_STGCLK_GRP0_MAIN … #define JH7110_STGCLK_GRP0_BUS … #define JH7110_STGCLK_GRP0_STG … #define JH7110_STGCLK_GRP1_MAIN … #define JH7110_STGCLK_GRP1_BUS … #define JH7110_STGCLK_GRP1_STG … #define JH7110_STGCLK_GRP1_HIFI … #define JH7110_STGCLK_E2_RTC … #define JH7110_STGCLK_E2_CORE … #define JH7110_STGCLK_E2_DBG … #define JH7110_STGCLK_DMA1P_AXI … #define JH7110_STGCLK_DMA1P_AHB … #define JH7110_STGCLK_END … /* ISPCRG clocks */ #define JH7110_ISPCLK_DOM4_APB_FUNC … #define JH7110_ISPCLK_MIPI_RX0_PXL … #define JH7110_ISPCLK_DVP_INV … #define JH7110_ISPCLK_M31DPHY_CFG_IN … #define JH7110_ISPCLK_M31DPHY_REF_IN … #define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 … #define JH7110_ISPCLK_VIN_APB … #define JH7110_ISPCLK_VIN_SYS … #define JH7110_ISPCLK_VIN_PIXEL_IF0 … #define JH7110_ISPCLK_VIN_PIXEL_IF1 … #define JH7110_ISPCLK_VIN_PIXEL_IF2 … #define JH7110_ISPCLK_VIN_PIXEL_IF3 … #define JH7110_ISPCLK_VIN_P_AXI_WR … #define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C … #define JH7110_ISPCLK_END … /* VOUTCRG clocks */ #define JH7110_VOUTCLK_APB … #define JH7110_VOUTCLK_DC8200_PIX … #define JH7110_VOUTCLK_DSI_SYS … #define JH7110_VOUTCLK_TX_ESC … #define JH7110_VOUTCLK_DC8200_AXI … #define JH7110_VOUTCLK_DC8200_CORE … #define JH7110_VOUTCLK_DC8200_AHB … #define JH7110_VOUTCLK_DC8200_PIX0 … #define JH7110_VOUTCLK_DC8200_PIX1 … #define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD … #define JH7110_VOUTCLK_DSITX_APB … #define JH7110_VOUTCLK_DSITX_SYS … #define JH7110_VOUTCLK_DSITX_DPI … #define JH7110_VOUTCLK_DSITX_TXESC … #define JH7110_VOUTCLK_MIPITX_DPHY_TXESC … #define JH7110_VOUTCLK_HDMI_TX_MCLK … #define JH7110_VOUTCLK_HDMI_TX_BCLK … #define JH7110_VOUTCLK_HDMI_TX_SYS … #define JH7110_VOUTCLK_END … #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
Codebase Browser
linux