linux/arch/x86/pci/acpi.c

// SPDX-License-Identifier: GPL-2.0

#define pr_fmt(fmt) …

#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/dmi.h>
#include <linux/slab.h>
#include <linux/pci-acpi.h>
#include <asm/numa.h>
#include <asm/pci_x86.h>

struct pci_root_info { … };

bool pci_use_e820 = …;
static bool pci_use_crs = …;
static bool pci_ignore_seg;

static int __init set_use_crs(const struct dmi_system_id *id)
{ … }

static int __init set_nouse_crs(const struct dmi_system_id *id)
{ … }

static int __init set_ignore_seg(const struct dmi_system_id *id)
{ … }

static int __init set_no_e820(const struct dmi_system_id *id)
{ … }

static const struct dmi_system_id pci_crs_quirks[] __initconst = …;

void __init pci_acpi_crs_quirks(void)
{ … }

#ifdef	CONFIG_PCI_MMCONFIG
static int check_segment(u16 seg, struct device *dev, char *estr)
{ … }

static int setup_mcfg_map(struct acpi_pci_root_info *ci)
{ … }

static void teardown_mcfg_map(struct acpi_pci_root_info *ci)
{ … }
#else
static int setup_mcfg_map(struct acpi_pci_root_info *ci)
{
	return 0;
}

static void teardown_mcfg_map(struct acpi_pci_root_info *ci)
{
}
#endif

static int pci_acpi_root_get_node(struct acpi_pci_root *root)
{ … }

static int pci_acpi_root_init_info(struct acpi_pci_root_info *ci)
{ … }

static void pci_acpi_root_release_info(struct acpi_pci_root_info *ci)
{ … }

/*
 * An IO port or MMIO resource assigned to a PCI host bridge may be
 * consumed by the host bridge itself or available to its child
 * bus/devices. The ACPI specification defines a bit (Producer/Consumer)
 * to tell whether the resource is consumed by the host bridge itself,
 * but firmware hasn't used that bit consistently, so we can't rely on it.
 *
 * On x86 and IA64 platforms, all IO port and MMIO resources are assumed
 * to be available to child bus/devices except one special case:
 *     IO port [0xCF8-0xCFF] is consumed by the host bridge itself
 *     to access PCI configuration space.
 *
 * So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
 */
static bool resource_is_pcicfg_ioport(struct resource *res)
{ … }

static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
{ … }

static struct acpi_pci_root_ops acpi_pci_root_ops = …;

struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
{ … }

int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
{ … }

int __init pci_acpi_init(void)
{ … }