// SPDX-License-Identifier: GPL-2.0 /* * Intel MID PCI support * Copyright (c) 2008 Intel Corporation * Jesse Barnes <[email protected]> * * Moorestown has an interesting PCI implementation: * - configuration space is memory mapped (as defined by MCFG) * - Lincroft devices also have a real, type 1 configuration space * - Early Lincroft silicon has a type 1 access bug that will cause * a hang if non-existent devices are accessed * - some devices have the "fixed BAR" capability, which means * they can't be relocated or modified; check for that during * BAR sizing * * So, we use the MCFG space for all reads and writes, but also send * Lincroft writes to type 1 space. But only read/write if the device * actually exists, otherwise return all 1s for reads and bit bucket * the writes. */ #include <linux/sched.h> #include <linux/pci.h> #include <linux/ioport.h> #include <linux/init.h> #include <linux/dmi.h> #include <linux/acpi.h> #include <linux/io.h> #include <linux/smp.h> #include <asm/cpu_device_id.h> #include <asm/segment.h> #include <asm/pci_x86.h> #include <asm/hw_irq.h> #include <asm/io_apic.h> #include <asm/intel-family.h> #include <asm/intel-mid.h> #include <asm/acpi.h> #define PCIE_CAP_OFFSET … /* Quirks for the listed devices */ #define PCI_DEVICE_ID_INTEL_MRFLD_MMC … #define PCI_DEVICE_ID_INTEL_MRFLD_HSU … /* Fixed BAR fields */ #define PCIE_VNDR_CAP_ID_FIXED_BAR … #define PCI_FIXED_BAR_0_SIZE … #define PCI_FIXED_BAR_1_SIZE … #define PCI_FIXED_BAR_2_SIZE … #define PCI_FIXED_BAR_3_SIZE … #define PCI_FIXED_BAR_4_SIZE … #define PCI_FIXED_BAR_5_SIZE … static int pci_soc_mode; /** * fixed_bar_cap - return the offset of the fixed BAR cap if found * @bus: PCI bus * @devfn: device in question * * Look for the fixed BAR cap on @bus and @devfn, returning its offset * if found or 0 otherwise. */ static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn) { … } static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn, int reg, int len, u32 val, int offset) { … } /** * type1_access_ok - check whether to use type 1 * @bus: bus number * @devfn: device & function in question * @reg: configuration register offset * * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at * all, the we can go ahead with any reads & writes. If it's on a Lincroft, * but doesn't exist, avoid the access altogether to keep the chip from * hanging. */ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) { … } static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { … } static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { … } static const struct x86_cpu_id intel_mid_cpu_ids[] = …; static int intel_mid_pci_irq_enable(struct pci_dev *dev) { … } static void intel_mid_pci_irq_disable(struct pci_dev *dev) { … } static const struct pci_ops intel_mid_pci_ops __initconst = …; /** * intel_mid_pci_init - installs intel_mid_pci_ops * * Moorestown has an interesting PCI implementation (see above). * Called when the early platform detection installs it. */ int __init intel_mid_pci_init(void) { … } /* * Langwell devices are not true PCI devices; they are not subject to 10 ms * d3 to d0 delay required by PCI spec. */ static void pci_d3delay_fixup(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup); static void mid_power_off_one_device(struct pci_dev *dev) { … } static void mid_power_off_devices(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices); /* * Langwell devices reside at fixed offsets, don't try to move them. */ static void pci_fixed_bar_fixup(struct pci_dev *dev) { … } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);
Codebase Browser
linux