linux/arch/x86/pci/amd_bus.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/topology.h>
#include <linux/cpu.h>
#include <linux/range.h>

#include <asm/amd_nb.h>
#include <asm/pci_x86.h>

#include <asm/pci-direct.h>

#include "bus_numa.h"

#define AMD_NB_F0_NODE_ID …
#define AMD_NB_F0_UNIT_ID …
#define AMD_NB_F1_CONFIG_MAP_REG …

#define RANGE_NUM …
#define AMD_NB_F1_CONFIG_MAP_RANGES …

struct amd_hostbridge { … };

/*
 * IMPORTANT NOTE:
 * hb_probes[] and early_root_info_init() is in maintenance mode.
 * It only supports K8, Fam10h, Fam11h, and Fam15h_00h-0fh .
 * Future processor will rely on information in ACPI.
 */
static struct amd_hostbridge hb_probes[] __initdata = …;

static struct pci_root_info __init *find_pci_root_info(int node, int link)
{ … }

static inline resource_size_t cap_resource(u64 val)
{ … }

/**
 * early_root_info_init()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according
 * to the LDT Bus Number Registers found in the northbridge.
 */
static int __init early_root_info_init(void)
{ … }

#define ENABLE_CF8_EXT_CFG …

static int amd_bus_cpu_online(unsigned int cpu)
{ … }

static void __init pci_enable_pci_io_ecs(void)
{ … }

static int __init pci_io_ecs_init(void)
{ … }

static int __init amd_postcore_init(void)
{ … }

postcore_initcall(amd_postcore_init);