linux/arch/x86/events/intel/uncore_discovery.h

/* SPDX-License-Identifier: GPL-2.0-only */

/* Generic device ID of a discovery table device */
#define UNCORE_DISCOVERY_TABLE_DEVICE …
/* Capability ID for a discovery table device */
#define UNCORE_EXT_CAP_ID_DISCOVERY …
/* First DVSEC offset */
#define UNCORE_DISCOVERY_DVSEC_OFFSET …
/* Mask of the supported discovery entry type */
#define UNCORE_DISCOVERY_DVSEC_ID_MASK …
/* PMON discovery entry type ID */
#define UNCORE_DISCOVERY_DVSEC_ID_PMON …
/* Second DVSEC offset */
#define UNCORE_DISCOVERY_DVSEC2_OFFSET …
/* Mask of the discovery table BAR offset */
#define UNCORE_DISCOVERY_DVSEC2_BIR_MASK …
/* Discovery table BAR base offset */
#define UNCORE_DISCOVERY_BIR_BASE …
/* Discovery table BAR step */
#define UNCORE_DISCOVERY_BIR_STEP …
/* Global discovery table size */
#define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE …

#define UNCORE_DISCOVERY_PCI_DOMAIN_OFFSET …
#define UNCORE_DISCOVERY_PCI_DOMAIN(data) …
#define UNCORE_DISCOVERY_PCI_BUS_OFFSET …
#define UNCORE_DISCOVERY_PCI_BUS(data) …
#define UNCORE_DISCOVERY_PCI_DEVFN_OFFSET …
#define UNCORE_DISCOVERY_PCI_DEVFN(data) …
#define UNCORE_DISCOVERY_PCI_BOX_CTRL(data) …


#define uncore_discovery_invalid_unit(unit) …

#define GENERIC_PMON_CTL_EV_SEL_MASK …
#define GENERIC_PMON_CTL_UMASK_MASK …
#define GENERIC_PMON_CTL_EDGE_DET …
#define GENERIC_PMON_CTL_INVERT …
#define GENERIC_PMON_CTL_TRESH_MASK …
#define GENERIC_PMON_RAW_EVENT_MASK …

#define GENERIC_PMON_BOX_CTL_FRZ …
#define GENERIC_PMON_BOX_CTL_RST_CTRL …
#define GENERIC_PMON_BOX_CTL_RST_CTRS …
#define GENERIC_PMON_BOX_CTL_INT …

enum uncore_access_type { … };

struct uncore_global_discovery { … };

struct uncore_unit_discovery { … };

struct intel_uncore_discovery_unit { … };

struct intel_uncore_discovery_type { … };

bool intel_uncore_has_discovery_tables(int *ignore);
void intel_uncore_clear_discovery_tables(void);
void intel_uncore_generic_uncore_cpu_init(void);
int intel_uncore_generic_uncore_pci_init(void);
void intel_uncore_generic_uncore_mmio_init(void);

void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box);
void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box);
void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box);

void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box);
void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box);
void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box);
void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,
					     struct perf_event *event);
void intel_generic_uncore_mmio_enable_event(struct intel_uncore_box *box,
					    struct perf_event *event);

void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);
void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);
void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);
void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
					    struct perf_event *event);
u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
					  struct perf_event *event);

struct intel_uncore_type **
intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num_extra);

int intel_uncore_find_discovery_unit_id(struct rb_root *units, int die,
					unsigned int pmu_idx);
bool intel_generic_uncore_assign_hw_event(struct perf_event *event,
					  struct intel_uncore_box *box);
void uncore_find_add_unit(struct intel_uncore_discovery_unit *node,
			  struct rb_root *root, u16 *num_units);