/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (C) 2020 Intel Corporation. * Lei Chuanhua <[email protected]> * Zhu Yixin <[email protected]> */ #ifndef __INTEL_LGM_CLK_H #define __INTEL_LGM_CLK_H /* PLL clocks */ #define LGM_CLK_OSC … #define LGM_CLK_PLLPP … #define LGM_CLK_PLL2 … #define LGM_CLK_PLL0CZ … #define LGM_CLK_PLL0B … #define LGM_CLK_PLL1 … #define LGM_CLK_LJPLL3 … #define LGM_CLK_LJPLL4 … #define LGM_CLK_PLL0CM0 … #define LGM_CLK_PLL0CM1 … /* clocks from PLLs */ /* ROPLL clocks */ #define LGM_CLK_PP_HW … #define LGM_CLK_PP_UC … #define LGM_CLK_PP_FXD … #define LGM_CLK_PP_TBM … /* PLL2 clocks */ #define LGM_CLK_DDR … /* PLL0CZ */ #define LGM_CLK_CM … #define LGM_CLK_IC … #define LGM_CLK_SDXC3 … /* PLL0B */ #define LGM_CLK_NGI … #define LGM_CLK_NOC4 … #define LGM_CLK_SW … #define LGM_CLK_QSPI … #define LGM_CLK_CQEM … #define LGM_CLK_EMMC5 … /* PLL1 */ #define LGM_CLK_CT … #define LGM_CLK_DSP … #define LGM_CLK_VIF … /* LJPLL3 */ #define LGM_CLK_CML … #define LGM_CLK_SERDES … #define LGM_CLK_POOL … #define LGM_CLK_PTP … /* LJPLL4 */ #define LGM_CLK_PCIE … #define LGM_CLK_SATA … /* PLL0CM0 */ #define LGM_CLK_CPU0 … /* PLL0CM1 */ #define LGM_CLK_CPU1 … /* Miscellaneous clocks */ #define LGM_CLK_EMMC4 … #define LGM_CLK_SDXC2 … #define LGM_CLK_EMMC … #define LGM_CLK_SDXC … #define LGM_CLK_SLIC … #define LGM_CLK_DCL … #define LGM_CLK_DOCSIS … #define LGM_CLK_PCM … #define LGM_CLK_DDR_PHY … #define LGM_CLK_PONDEF … #define LGM_CLK_PL25M … #define LGM_CLK_PL10M … #define LGM_CLK_PL1544K … #define LGM_CLK_PL2048K … #define LGM_CLK_PL8K … #define LGM_CLK_PON_NTR … #define LGM_CLK_SYNC0 … #define LGM_CLK_SYNC1 … #define LGM_CLK_PROGDIV … #define LGM_CLK_OD0 … #define LGM_CLK_OD1 … #define LGM_CLK_CBPHY0 … #define LGM_CLK_CBPHY1 … #define LGM_CLK_CBPHY2 … #define LGM_CLK_CBPHY3 … /* Gate clocks */ /* Gate CLK0 */ #define LGM_GCLK_C55 … #define LGM_GCLK_QSPI … #define LGM_GCLK_EIP197 … #define LGM_GCLK_VAULT … #define LGM_GCLK_TOE … #define LGM_GCLK_SDXC … #define LGM_GCLK_EMMC … #define LGM_GCLK_SPI_DBG … #define LGM_GCLK_DMA3 … /* Gate CLK1 */ #define LGM_GCLK_DMA0 … #define LGM_GCLK_LEDC0 … #define LGM_GCLK_LEDC1 … #define LGM_GCLK_I2S0 … #define LGM_GCLK_I2S1 … #define LGM_GCLK_EBU … #define LGM_GCLK_PWM … #define LGM_GCLK_I2C0 … #define LGM_GCLK_I2C1 … #define LGM_GCLK_I2C2 … #define LGM_GCLK_I2C3 … #define LGM_GCLK_SSC0 … #define LGM_GCLK_SSC1 … #define LGM_GCLK_SSC2 … #define LGM_GCLK_SSC3 … #define LGM_GCLK_GPTC0 … #define LGM_GCLK_GPTC1 … #define LGM_GCLK_GPTC2 … #define LGM_GCLK_GPTC3 … #define LGM_GCLK_ASC0 … #define LGM_GCLK_ASC1 … #define LGM_GCLK_ASC2 … #define LGM_GCLK_ASC3 … #define LGM_GCLK_PCM0 … #define LGM_GCLK_PCM1 … #define LGM_GCLK_PCM2 … /* Gate CLK2 */ #define LGM_GCLK_PCIE10 … #define LGM_GCLK_PCIE11 … #define LGM_GCLK_PCIE30 … #define LGM_GCLK_PCIE31 … #define LGM_GCLK_PCIE20 … #define LGM_GCLK_PCIE21 … #define LGM_GCLK_PCIE40 … #define LGM_GCLK_PCIE41 … #define LGM_GCLK_XPCS0 … #define LGM_GCLK_XPCS1 … #define LGM_GCLK_XPCS2 … #define LGM_GCLK_XPCS3 … #define LGM_GCLK_SATA0 … #define LGM_GCLK_SATA1 … #define LGM_GCLK_SATA2 … #define LGM_GCLK_SATA3 … /* Gate CLK3 */ #define LGM_GCLK_ARCEM4 … #define LGM_GCLK_IDMAR1 … #define LGM_GCLK_IDMAT0 … #define LGM_GCLK_IDMAT1 … #define LGM_GCLK_IDMAT2 … #define LGM_GCLK_PPV4 … #define LGM_GCLK_GSWIPO … #define LGM_GCLK_CQEM … #define LGM_GCLK_XPCS5 … #define LGM_GCLK_USB1 … #define LGM_GCLK_USB2 … #endif /* __INTEL_LGM_CLK_H */
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