/* * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer * * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1, * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve * basis. Clients can directly request any frequency that the chip can * deliver using the standard clk framework. In addition, the device can * be configured and activated via the devicetree. * * Copyright (C) 2014, Topic Embedded Products * Licenced under GPL */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/module.h> #include <linux/i2c.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/slab.h> #include <linux/gcd.h> /* Each chip has different number of PLLs and outputs, for example: * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs. * Model this as 2 PLL clocks which are parents to the outputs. */ struct clk_cdce925_chip_info { … }; #define MAX_NUMBER_OF_PLLS … #define MAX_NUMBER_OF_OUTPUTS … #define CDCE925_REG_GLOBAL1 … #define CDCE925_REG_Y1SPIPDIVH … #define CDCE925_REG_PDIVL … #define CDCE925_REG_XCSEL … /* PLL parameters start at 0x10, steps of 0x10 */ #define CDCE925_OFFSET_PLL … /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ #define CDCE925_PLL_MUX_OUTPUTS … #define CDCE925_PLL_MULDIV … #define CDCE925_PLL_FREQUENCY_MIN … #define CDCE925_PLL_FREQUENCY_MAX … struct clk_cdce925_chip; struct clk_cdce925_output { … }; #define to_clk_cdce925_output(_hw) … struct clk_cdce925_pll { … }; #define to_clk_cdce925_pll(_hw) … struct clk_cdce925_chip { … }; /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, u16 n, u16 m) { … } static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static void cdce925_pll_find_rate(unsigned long rate, unsigned long parent_rate, u16 *n, u16 *m) { … } static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } /* calculate p = max(0, 4 - int(log2 (n/m))) */ static u8 cdce925_pll_calc_p(u16 n, u16 m) { … } /* Returns VCO range bits for VCO1_0_RANGE */ static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) { … } /* I2C clock, hence everything must happen in (un)prepare because this * may sleep */ static int cdce925_pll_prepare(struct clk_hw *hw) { … } static void cdce925_pll_unprepare(struct clk_hw *hw) { … } static const struct clk_ops cdce925_pll_ops = …; static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) { … } static void cdce925_clk_activate(struct clk_cdce925_output *data) { … } static int cdce925_clk_prepare(struct clk_hw *hw) { … } static void cdce925_clk_unprepare(struct clk_hw *hw) { … } static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static u16 cdce925_calc_divider(unsigned long rate, unsigned long parent_rate) { … } static unsigned long cdce925_clk_best_parent_rate( struct clk_hw *hw, unsigned long rate) { … } static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops cdce925_clk_ops = …; static u16 cdce925_y1_calc_divider(unsigned long rate, unsigned long parent_rate) { … } static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops cdce925_clk_y1_ops = …; #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER … #define CDCE925_I2C_COMMAND_BYTE_TRANSFER … static int cdce925_regmap_i2c_write( void *context, const void *data, size_t count) { … } static int cdce925_regmap_i2c_read(void *context, const void *reg, size_t reg_size, void *val, size_t val_size) { … } static struct clk_hw * of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data) { … } static int cdce925_regulator_enable(struct device *dev, const char *name) { … } /* The CDCE925 uses a funky way to read/write registers. Bulk mode is * just weird, so just use the single byte mode exclusively. */ static struct regmap_bus regmap_cdce925_bus = …; static int cdce925_probe(struct i2c_client *client) { … } static const struct clk_cdce925_chip_info clk_cdce913_info = …; static const struct clk_cdce925_chip_info clk_cdce925_info = …; static const struct clk_cdce925_chip_info clk_cdce937_info = …; static const struct clk_cdce925_chip_info clk_cdce949_info = …; static const struct i2c_device_id cdce925_id[] = …; MODULE_DEVICE_TABLE(i2c, cdce925_id); static const struct of_device_id clk_cdce925_of_match[] = …; MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); static struct i2c_driver cdce925_driver = …; module_i2c_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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