// SPDX-License-Identifier: GPL-2.0 /* SandyBridge-EP/IvyTown uncore support */ #include <asm/cpu_device_id.h> #include "uncore.h" #include "uncore_discovery.h" /* SNB-EP pci bus to socket mapping */ #define SNBEP_CPUNODEID … #define SNBEP_GIDNIDMAP … /* SNB-EP Box level control */ #define SNBEP_PMON_BOX_CTL_RST_CTRL … #define SNBEP_PMON_BOX_CTL_RST_CTRS … #define SNBEP_PMON_BOX_CTL_FRZ … #define SNBEP_PMON_BOX_CTL_FRZ_EN … #define SNBEP_PMON_BOX_CTL_INT … /* SNB-EP event control */ #define SNBEP_PMON_CTL_EV_SEL_MASK … #define SNBEP_PMON_CTL_UMASK_MASK … #define SNBEP_PMON_CTL_RST … #define SNBEP_PMON_CTL_EDGE_DET … #define SNBEP_PMON_CTL_EV_SEL_EXT … #define SNBEP_PMON_CTL_EN … #define SNBEP_PMON_CTL_INVERT … #define SNBEP_PMON_CTL_TRESH_MASK … #define SNBEP_PMON_RAW_EVENT_MASK … /* SNB-EP Ubox event control */ #define SNBEP_U_MSR_PMON_CTL_TRESH_MASK … #define SNBEP_U_MSR_PMON_RAW_EVENT_MASK … #define SNBEP_CBO_PMON_CTL_TID_EN … #define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK … /* SNB-EP PCU event control */ #define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK … #define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK … #define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT … #define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET … #define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK … #define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK … /* SNB-EP pci control register */ #define SNBEP_PCI_PMON_BOX_CTL … #define SNBEP_PCI_PMON_CTL0 … /* SNB-EP pci counter register */ #define SNBEP_PCI_PMON_CTR0 … /* SNB-EP home agent register */ #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 … #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 … #define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH … /* SNB-EP memory controller register */ #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL … #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR … /* SNB-EP QPI register */ #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 … #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 … #define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 … #define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 … /* SNB-EP Ubox register */ #define SNBEP_U_MSR_PMON_CTR0 … #define SNBEP_U_MSR_PMON_CTL0 … #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL … #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR … /* SNB-EP Cbo register */ #define SNBEP_C0_MSR_PMON_CTR0 … #define SNBEP_C0_MSR_PMON_CTL0 … #define SNBEP_C0_MSR_PMON_BOX_CTL … #define SNBEP_C0_MSR_PMON_BOX_FILTER … #define SNBEP_CBO_MSR_OFFSET … #define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID … #define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID … #define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE … #define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC … #define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) … /* SNB-EP PCU register */ #define SNBEP_PCU_MSR_PMON_CTR0 … #define SNBEP_PCU_MSR_PMON_CTL0 … #define SNBEP_PCU_MSR_PMON_BOX_CTL … #define SNBEP_PCU_MSR_PMON_BOX_FILTER … #define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK … #define SNBEP_PCU_MSR_CORE_C3_CTR … #define SNBEP_PCU_MSR_CORE_C6_CTR … /* IVBEP event control */ #define IVBEP_PMON_BOX_CTL_INT … #define IVBEP_PMON_RAW_EVENT_MASK … /* IVBEP Ubox */ #define IVBEP_U_MSR_PMON_GLOBAL_CTL … #define IVBEP_U_PMON_GLOBAL_FRZ_ALL … #define IVBEP_U_PMON_GLOBAL_UNFRZ_ALL … #define IVBEP_U_MSR_PMON_RAW_EVENT_MASK … /* IVBEP Cbo */ #define IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK … #define IVBEP_CB0_MSR_PMON_BOX_FILTER_TID … #define IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK … #define IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE … #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NID … #define IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC … #define IVBEP_CB0_MSR_PMON_BOX_FILTER_C6 … #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NC … #define IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC … /* IVBEP home agent */ #define IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST … #define IVBEP_HA_PCI_PMON_RAW_EVENT_MASK … /* IVBEP PCU */ #define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK … /* IVBEP QPI */ #define IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK … #define __BITS_VALUE(x, i, n) … /* Haswell-EP Ubox */ #define HSWEP_U_MSR_PMON_CTR0 … #define HSWEP_U_MSR_PMON_CTL0 … #define HSWEP_U_MSR_PMON_FILTER … #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL … #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTR … #define HSWEP_U_MSR_PMON_BOX_FILTER_TID … #define HSWEP_U_MSR_PMON_BOX_FILTER_CID … #define HSWEP_U_MSR_PMON_BOX_FILTER_MASK … /* Haswell-EP CBo */ #define HSWEP_C0_MSR_PMON_CTR0 … #define HSWEP_C0_MSR_PMON_CTL0 … #define HSWEP_C0_MSR_PMON_BOX_CTL … #define HSWEP_C0_MSR_PMON_BOX_FILTER0 … #define HSWEP_CBO_MSR_OFFSET … #define HSWEP_CB0_MSR_PMON_BOX_FILTER_TID … #define HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK … #define HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE … #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NID … #define HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC … #define HSWEP_CB0_MSR_PMON_BOX_FILTER_C6 … #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NC … #define HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC … /* Haswell-EP Sbox */ #define HSWEP_S0_MSR_PMON_CTR0 … #define HSWEP_S0_MSR_PMON_CTL0 … #define HSWEP_S0_MSR_PMON_BOX_CTL … #define HSWEP_SBOX_MSR_OFFSET … #define HSWEP_S_MSR_PMON_RAW_EVENT_MASK … /* Haswell-EP PCU */ #define HSWEP_PCU_MSR_PMON_CTR0 … #define HSWEP_PCU_MSR_PMON_CTL0 … #define HSWEP_PCU_MSR_PMON_BOX_CTL … #define HSWEP_PCU_MSR_PMON_BOX_FILTER … /* KNL Ubox */ #define KNL_U_MSR_PMON_RAW_EVENT_MASK … /* KNL CHA */ #define KNL_CHA_MSR_OFFSET … #define KNL_CHA_MSR_PMON_CTL_QOR … #define KNL_CHA_MSR_PMON_RAW_EVENT_MASK … #define KNL_CHA_MSR_PMON_BOX_FILTER_TID … #define KNL_CHA_MSR_PMON_BOX_FILTER_STATE … #define KNL_CHA_MSR_PMON_BOX_FILTER_OP … #define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE … #define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE … #define KNL_CHA_MSR_PMON_BOX_FILTER_NNC … /* KNL EDC/MC UCLK */ #define KNL_UCLK_MSR_PMON_CTR0_LOW … #define KNL_UCLK_MSR_PMON_CTL0 … #define KNL_UCLK_MSR_PMON_BOX_CTL … #define KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW … #define KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL … #define KNL_PMON_FIXED_CTL_EN … /* KNL EDC */ #define KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW … #define KNL_EDC0_ECLK_MSR_PMON_CTL0 … #define KNL_EDC0_ECLK_MSR_PMON_BOX_CTL … #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW … #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL … /* KNL MC */ #define KNL_MC0_CH0_MSR_PMON_CTR0_LOW … #define KNL_MC0_CH0_MSR_PMON_CTL0 … #define KNL_MC0_CH0_MSR_PMON_BOX_CTL … #define KNL_MC0_CH0_MSR_PMON_FIXED_LOW … #define KNL_MC0_CH0_MSR_PMON_FIXED_CTL … /* KNL IRP */ #define KNL_IRP_PCI_PMON_BOX_CTL … #define KNL_IRP_PCI_PMON_RAW_EVENT_MASK … /* KNL PCU */ #define KNL_PCU_PMON_CTL_EV_SEL_MASK … #define KNL_PCU_PMON_CTL_USE_OCC_CTR … #define KNL_PCU_MSR_PMON_CTL_TRESH_MASK … #define KNL_PCU_MSR_PMON_RAW_EVENT_MASK … /* SKX pci bus to socket mapping */ #define SKX_CPUNODEID … #define SKX_GIDNIDMAP … /* * The CPU_BUS_NUMBER MSR returns the values of the respective CPUBUSNO CSR * that BIOS programmed. MSR has package scope. * | Bit | Default | Description * | [63] | 00h | VALID - When set, indicates the CPU bus * numbers have been initialized. (RO) * |[62:48]| --- | Reserved * |[47:40]| 00h | BUS_NUM_5 - Return the bus number BIOS assigned * CPUBUSNO(5). (RO) * |[39:32]| 00h | BUS_NUM_4 - Return the bus number BIOS assigned * CPUBUSNO(4). (RO) * |[31:24]| 00h | BUS_NUM_3 - Return the bus number BIOS assigned * CPUBUSNO(3). (RO) * |[23:16]| 00h | BUS_NUM_2 - Return the bus number BIOS assigned * CPUBUSNO(2). (RO) * |[15:8] | 00h | BUS_NUM_1 - Return the bus number BIOS assigned * CPUBUSNO(1). (RO) * | [7:0] | 00h | BUS_NUM_0 - Return the bus number BIOS assigned * CPUBUSNO(0). (RO) */ #define SKX_MSR_CPU_BUS_NUMBER … #define SKX_MSR_CPU_BUS_VALID_BIT … #define BUS_NUM_STRIDE … /* SKX CHA */ #define SKX_CHA_MSR_PMON_BOX_FILTER_TID … #define SKX_CHA_MSR_PMON_BOX_FILTER_LINK … #define SKX_CHA_MSR_PMON_BOX_FILTER_STATE … #define SKX_CHA_MSR_PMON_BOX_FILTER_REM … #define SKX_CHA_MSR_PMON_BOX_FILTER_LOC … #define SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC … #define SKX_CHA_MSR_PMON_BOX_FILTER_NM … #define SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM … #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC0 … #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC1 … #define SKX_CHA_MSR_PMON_BOX_FILTER_C6 … #define SKX_CHA_MSR_PMON_BOX_FILTER_NC … #define SKX_CHA_MSR_PMON_BOX_FILTER_ISOC … /* SKX IIO */ #define SKX_IIO0_MSR_PMON_CTL0 … #define SKX_IIO0_MSR_PMON_CTR0 … #define SKX_IIO0_MSR_PMON_BOX_CTL … #define SKX_IIO_MSR_OFFSET … #define SKX_PMON_CTL_TRESH_MASK … #define SKX_PMON_CTL_TRESH_MASK_EXT … #define SKX_PMON_CTL_CH_MASK … #define SKX_PMON_CTL_FC_MASK … #define SKX_IIO_PMON_RAW_EVENT_MASK … #define SKX_IIO_PMON_RAW_EVENT_MASK_EXT … /* SKX IRP */ #define SKX_IRP0_MSR_PMON_CTL0 … #define SKX_IRP0_MSR_PMON_CTR0 … #define SKX_IRP0_MSR_PMON_BOX_CTL … #define SKX_IRP_MSR_OFFSET … /* SKX UPI */ #define SKX_UPI_PCI_PMON_CTL0 … #define SKX_UPI_PCI_PMON_CTR0 … #define SKX_UPI_PCI_PMON_BOX_CTL … #define SKX_UPI_CTL_UMASK_EXT … /* SKX M2M */ #define SKX_M2M_PCI_PMON_CTL0 … #define SKX_M2M_PCI_PMON_CTR0 … #define SKX_M2M_PCI_PMON_BOX_CTL … /* Memory Map registers device ID */ #define SNR_ICX_MESH2IIO_MMAP_DID … #define SNR_ICX_SAD_CONTROL_CFG … /* Getting I/O stack id in SAD_COTROL_CFG notation */ #define SAD_CONTROL_STACK_ID(data) … /* SNR Ubox */ #define SNR_U_MSR_PMON_CTR0 … #define SNR_U_MSR_PMON_CTL0 … #define SNR_U_MSR_PMON_UCLK_FIXED_CTL … #define SNR_U_MSR_PMON_UCLK_FIXED_CTR … /* SNR CHA */ #define SNR_CHA_RAW_EVENT_MASK_EXT … #define SNR_CHA_MSR_PMON_CTL0 … #define SNR_CHA_MSR_PMON_CTR0 … #define SNR_CHA_MSR_PMON_BOX_CTL … #define SNR_C0_MSR_PMON_BOX_FILTER0 … /* SNR IIO */ #define SNR_IIO_MSR_PMON_CTL0 … #define SNR_IIO_MSR_PMON_CTR0 … #define SNR_IIO_MSR_PMON_BOX_CTL … #define SNR_IIO_MSR_OFFSET … #define SNR_IIO_PMON_RAW_EVENT_MASK_EXT … /* SNR IRP */ #define SNR_IRP0_MSR_PMON_CTL0 … #define SNR_IRP0_MSR_PMON_CTR0 … #define SNR_IRP0_MSR_PMON_BOX_CTL … #define SNR_IRP_MSR_OFFSET … /* SNR M2PCIE */ #define SNR_M2PCIE_MSR_PMON_CTL0 … #define SNR_M2PCIE_MSR_PMON_CTR0 … #define SNR_M2PCIE_MSR_PMON_BOX_CTL … #define SNR_M2PCIE_MSR_OFFSET … /* SNR PCU */ #define SNR_PCU_MSR_PMON_CTL0 … #define SNR_PCU_MSR_PMON_CTR0 … #define SNR_PCU_MSR_PMON_BOX_CTL … #define SNR_PCU_MSR_PMON_BOX_FILTER … /* SNR M2M */ #define SNR_M2M_PCI_PMON_CTL0 … #define SNR_M2M_PCI_PMON_CTR0 … #define SNR_M2M_PCI_PMON_BOX_CTL … #define SNR_M2M_PCI_PMON_UMASK_EXT … /* SNR PCIE3 */ #define SNR_PCIE3_PCI_PMON_CTL0 … #define SNR_PCIE3_PCI_PMON_CTR0 … #define SNR_PCIE3_PCI_PMON_BOX_CTL … /* SNR IMC */ #define SNR_IMC_MMIO_PMON_FIXED_CTL … #define SNR_IMC_MMIO_PMON_FIXED_CTR … #define SNR_IMC_MMIO_PMON_CTL0 … #define SNR_IMC_MMIO_PMON_CTR0 … #define SNR_IMC_MMIO_PMON_BOX_CTL … #define SNR_IMC_MMIO_OFFSET … #define SNR_IMC_MMIO_SIZE … #define SNR_IMC_MMIO_BASE_OFFSET … #define SNR_IMC_MMIO_BASE_MASK … #define SNR_IMC_MMIO_MEM0_OFFSET … #define SNR_IMC_MMIO_MEM0_MASK … /* ICX CHA */ #define ICX_C34_MSR_PMON_CTR0 … #define ICX_C34_MSR_PMON_CTL0 … #define ICX_C34_MSR_PMON_BOX_CTL … #define ICX_C34_MSR_PMON_BOX_FILTER0 … /* ICX IIO */ #define ICX_IIO_MSR_PMON_CTL0 … #define ICX_IIO_MSR_PMON_CTR0 … #define ICX_IIO_MSR_PMON_BOX_CTL … /* ICX IRP */ #define ICX_IRP0_MSR_PMON_CTL0 … #define ICX_IRP0_MSR_PMON_CTR0 … #define ICX_IRP0_MSR_PMON_BOX_CTL … /* ICX M2PCIE */ #define ICX_M2PCIE_MSR_PMON_CTL0 … #define ICX_M2PCIE_MSR_PMON_CTR0 … #define ICX_M2PCIE_MSR_PMON_BOX_CTL … /* ICX UPI */ #define ICX_UPI_PCI_PMON_CTL0 … #define ICX_UPI_PCI_PMON_CTR0 … #define ICX_UPI_PCI_PMON_BOX_CTL … #define ICX_UPI_CTL_UMASK_EXT … #define ICX_UBOX_DID … /* ICX M3UPI*/ #define ICX_M3UPI_PCI_PMON_CTL0 … #define ICX_M3UPI_PCI_PMON_CTR0 … #define ICX_M3UPI_PCI_PMON_BOX_CTL … /* ICX IMC */ #define ICX_NUMBER_IMC_CHN … #define ICX_IMC_MEM_STRIDE … /* SPR */ #define SPR_RAW_EVENT_MASK_EXT … #define SPR_UBOX_DID … /* SPR CHA */ #define SPR_CHA_EVENT_MASK_EXT … #define SPR_CHA_PMON_CTL_TID_EN … #define SPR_CHA_PMON_EVENT_MASK … #define SPR_CHA_PMON_BOX_FILTER_TID … #define SPR_C0_MSR_PMON_BOX_FILTER0 … DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); DEFINE_UNCORE_FORMAT_ATTR(…); static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box) { … } static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box) { … } static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event) { … } static void snbep_uncore_pci_init_box(struct intel_uncore_box *box) { … } static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box) { … } static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box) { … } static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void snbep_uncore_msr_init_box(struct intel_uncore_box *box) { … } static struct attribute *snbep_uncore_formats_attr[] = …; static struct attribute *snbep_uncore_ubox_formats_attr[] = …; static struct attribute *snbep_uncore_cbox_formats_attr[] = …; static struct attribute *snbep_uncore_pcu_formats_attr[] = …; static struct attribute *snbep_uncore_qpi_formats_attr[] = …; static struct uncore_event_desc snbep_uncore_imc_events[] = …; static struct uncore_event_desc snbep_uncore_qpi_events[] = …; static const struct attribute_group snbep_uncore_format_group = …; static const struct attribute_group snbep_uncore_ubox_format_group = …; static const struct attribute_group snbep_uncore_cbox_format_group = …; static const struct attribute_group snbep_uncore_pcu_format_group = …; static const struct attribute_group snbep_uncore_qpi_format_group = …; #define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT() … #define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() … \ static struct intel_uncore_ops snbep_uncore_msr_ops = …; #define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() … static struct intel_uncore_ops snbep_uncore_pci_ops = …; static struct event_constraint snbep_uncore_cbox_constraints[] = …; static struct event_constraint snbep_uncore_r2pcie_constraints[] = …; static struct event_constraint snbep_uncore_r3qpi_constraints[] = …; static struct intel_uncore_type snbep_uncore_ubox = …; static struct extra_reg snbep_uncore_cbox_extra_regs[] = …; static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static struct event_constraint * __snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event, u64 (*cbox_filter_mask)(int fields)) { … } static u64 snbep_cbox_filter_mask(int fields) { … } static struct event_constraint * snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops snbep_uncore_cbox_ops = …; static struct intel_uncore_type snbep_uncore_cbox = …; static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify) { … } static struct event_constraint * snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops snbep_uncore_pcu_ops = …; static struct intel_uncore_type snbep_uncore_pcu = …; static struct intel_uncore_type *snbep_msr_uncores[] = …; void snbep_uncore_cpu_init(void) { … } enum { … }; static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops snbep_uncore_qpi_ops = …; #define SNBEP_UNCORE_PCI_COMMON_INIT() … static struct intel_uncore_type snbep_uncore_ha = …; static struct intel_uncore_type snbep_uncore_imc = …; static struct intel_uncore_type snbep_uncore_qpi = …; static struct intel_uncore_type snbep_uncore_r2pcie = …; static struct intel_uncore_type snbep_uncore_r3qpi = …; enum { … }; static struct intel_uncore_type *snbep_pci_uncores[] = …; static const struct pci_device_id snbep_uncore_pci_ids[] = …; static struct pci_driver snbep_uncore_pci_driver = …; #define NODE_ID_MASK … /* Each three bits from 0 to 23 of GIDNIDMAP register correspond Node ID. */ #define GIDNIDMAP(config, id) … static int upi_nodeid_groupid(struct pci_dev *ubox_dev, int nodeid_loc, int idmap_loc, int *nodeid, int *groupid) { … } static int topology_gidnid_map(int nodeid, u32 gidnid) { … } /* * build pci bus to socket mapping */ static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool reverse) { … } int snbep_uncore_pci_init(void) { … } /* end of Sandy Bridge-EP uncore support */ /* IvyTown uncore support */ static void ivbep_uncore_msr_init_box(struct intel_uncore_box *box) { … } static void ivbep_uncore_pci_init_box(struct intel_uncore_box *box) { … } #define IVBEP_UNCORE_MSR_OPS_COMMON_INIT() … static struct intel_uncore_ops ivbep_uncore_msr_ops = …; static struct intel_uncore_ops ivbep_uncore_pci_ops = …; #define IVBEP_UNCORE_PCI_COMMON_INIT() … static struct attribute *ivbep_uncore_formats_attr[] = …; static struct attribute *ivbep_uncore_ubox_formats_attr[] = …; static struct attribute *ivbep_uncore_cbox_formats_attr[] = …; static struct attribute *ivbep_uncore_pcu_formats_attr[] = …; static struct attribute *ivbep_uncore_qpi_formats_attr[] = …; static const struct attribute_group ivbep_uncore_format_group = …; static const struct attribute_group ivbep_uncore_ubox_format_group = …; static const struct attribute_group ivbep_uncore_cbox_format_group = …; static const struct attribute_group ivbep_uncore_pcu_format_group = …; static const struct attribute_group ivbep_uncore_qpi_format_group = …; static struct intel_uncore_type ivbep_uncore_ubox = …; static struct extra_reg ivbep_uncore_cbox_extra_regs[] = …; static u64 ivbep_cbox_filter_mask(int fields) { … } static struct event_constraint * ivbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static int ivbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static void ivbep_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops ivbep_uncore_cbox_ops = …; static struct intel_uncore_type ivbep_uncore_cbox = …; static struct intel_uncore_ops ivbep_uncore_pcu_ops = …; static struct intel_uncore_type ivbep_uncore_pcu = …; static struct intel_uncore_type *ivbep_msr_uncores[] = …; void ivbep_uncore_cpu_init(void) { … } static struct intel_uncore_type ivbep_uncore_ha = …; static struct intel_uncore_type ivbep_uncore_imc = …; /* registers in IRP boxes are not properly aligned */ static unsigned ivbep_uncore_irp_ctls[] = …; static unsigned ivbep_uncore_irp_ctrs[] = …; static void ivbep_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void ivbep_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static u64 ivbep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops ivbep_uncore_irp_ops = …; static struct intel_uncore_type ivbep_uncore_irp = …; static struct intel_uncore_ops ivbep_uncore_qpi_ops = …; static struct intel_uncore_type ivbep_uncore_qpi = …; static struct intel_uncore_type ivbep_uncore_r2pcie = …; static struct intel_uncore_type ivbep_uncore_r3qpi = …; enum { … }; static struct intel_uncore_type *ivbep_pci_uncores[] = …; static const struct pci_device_id ivbep_uncore_pci_ids[] = …; static struct pci_driver ivbep_uncore_pci_driver = …; int ivbep_uncore_pci_init(void) { … } /* end of IvyTown uncore support */ /* KNL uncore support */ static struct attribute *knl_uncore_ubox_formats_attr[] = …; static const struct attribute_group knl_uncore_ubox_format_group = …; static struct intel_uncore_type knl_uncore_ubox = …; static struct attribute *knl_uncore_cha_formats_attr[] = …; static const struct attribute_group knl_uncore_cha_format_group = …; static struct event_constraint knl_uncore_cha_constraints[] = …; static struct extra_reg knl_uncore_cha_extra_regs[] = …; static u64 knl_cha_filter_mask(int fields) { … } static struct event_constraint * knl_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static int knl_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static void hswep_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event); static struct intel_uncore_ops knl_uncore_cha_ops = …; static struct intel_uncore_type knl_uncore_cha = …; static struct attribute *knl_uncore_pcu_formats_attr[] = …; static const struct attribute_group knl_uncore_pcu_format_group = …; static struct intel_uncore_type knl_uncore_pcu = …; static struct intel_uncore_type *knl_msr_uncores[] = …; void knl_uncore_cpu_init(void) { … } static void knl_uncore_imc_enable_box(struct intel_uncore_box *box) { … } static void knl_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops knl_uncore_imc_ops = …; static struct intel_uncore_type knl_uncore_imc_uclk = …; static struct intel_uncore_type knl_uncore_imc_dclk = …; static struct intel_uncore_type knl_uncore_edc_uclk = …; static struct intel_uncore_type knl_uncore_edc_eclk = …; static struct event_constraint knl_uncore_m2pcie_constraints[] = …; static struct intel_uncore_type knl_uncore_m2pcie = …; static struct attribute *knl_uncore_irp_formats_attr[] = …; static const struct attribute_group knl_uncore_irp_format_group = …; static struct intel_uncore_type knl_uncore_irp = …; enum { … }; static struct intel_uncore_type *knl_pci_uncores[] = …; /* * KNL uses a common PCI device ID for multiple instances of an Uncore PMU * device type. prior to KNL, each instance of a PMU device type had a unique * device ID. * * PCI Device ID Uncore PMU Devices * ---------------------------------- * 0x7841 MC0 UClk, MC1 UClk * 0x7843 MC0 DClk CH 0, MC0 DClk CH 1, MC0 DClk CH 2, * MC1 DClk CH 0, MC1 DClk CH 1, MC1 DClk CH 2 * 0x7833 EDC0 UClk, EDC1 UClk, EDC2 UClk, EDC3 UClk, * EDC4 UClk, EDC5 UClk, EDC6 UClk, EDC7 UClk * 0x7835 EDC0 EClk, EDC1 EClk, EDC2 EClk, EDC3 EClk, * EDC4 EClk, EDC5 EClk, EDC6 EClk, EDC7 EClk * 0x7817 M2PCIe * 0x7814 IRP */ static const struct pci_device_id knl_uncore_pci_ids[] = …; static struct pci_driver knl_uncore_pci_driver = …; int knl_uncore_pci_init(void) { … } /* end of KNL uncore support */ /* Haswell-EP uncore support */ static struct attribute *hswep_uncore_ubox_formats_attr[] = …; static const struct attribute_group hswep_uncore_ubox_format_group = …; static int hswep_ubox_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops hswep_uncore_ubox_ops = …; static struct intel_uncore_type hswep_uncore_ubox = …; static struct attribute *hswep_uncore_cbox_formats_attr[] = …; static const struct attribute_group hswep_uncore_cbox_format_group = …; static struct event_constraint hswep_uncore_cbox_constraints[] = …; static struct extra_reg hswep_uncore_cbox_extra_regs[] = …; static u64 hswep_cbox_filter_mask(int fields) { … } static struct event_constraint * hswep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static int hswep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static void hswep_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops hswep_uncore_cbox_ops = …; static struct intel_uncore_type hswep_uncore_cbox = …; /* * Write SBOX Initialization register bit by bit to avoid spurious #GPs */ static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = …; static struct attribute *hswep_uncore_sbox_formats_attr[] = …; static const struct attribute_group hswep_uncore_sbox_format_group = …; static struct intel_uncore_type hswep_uncore_sbox = …; static int hswep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops hswep_uncore_pcu_ops = …; static struct intel_uncore_type hswep_uncore_pcu = …; static struct intel_uncore_type *hswep_msr_uncores[] = …; #define HSWEP_PCU_DID … #define HSWEP_PCU_CAPID4_OFFET … #define hswep_get_chop(_cap) … static bool hswep_has_limit_sbox(unsigned int device) { … } void hswep_uncore_cpu_init(void) { … } static struct intel_uncore_type hswep_uncore_ha = …; static struct uncore_event_desc hswep_uncore_imc_events[] = …; static struct intel_uncore_type hswep_uncore_imc = …; static unsigned hswep_uncore_irp_ctrs[] = …; static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops hswep_uncore_irp_ops = …; static struct intel_uncore_type hswep_uncore_irp = …; static struct intel_uncore_type hswep_uncore_qpi = …; static struct event_constraint hswep_uncore_r2pcie_constraints[] = …; static struct intel_uncore_type hswep_uncore_r2pcie = …; static struct event_constraint hswep_uncore_r3qpi_constraints[] = …; static struct intel_uncore_type hswep_uncore_r3qpi = …; enum { … }; static struct intel_uncore_type *hswep_pci_uncores[] = …; static const struct pci_device_id hswep_uncore_pci_ids[] = …; static struct pci_driver hswep_uncore_pci_driver = …; int hswep_uncore_pci_init(void) { … } /* end of Haswell-EP uncore support */ /* BDX uncore support */ static struct intel_uncore_type bdx_uncore_ubox = …; static struct event_constraint bdx_uncore_cbox_constraints[] = …; static struct intel_uncore_type bdx_uncore_cbox = …; static struct intel_uncore_type bdx_uncore_sbox = …; #define BDX_MSR_UNCORE_SBOX … static struct intel_uncore_type *bdx_msr_uncores[] = …; /* Bit 7 'Use Occupancy' is not available for counter 0 on BDX */ static struct event_constraint bdx_uncore_pcu_constraints[] = …; #define BDX_PCU_DID … void bdx_uncore_cpu_init(void) { … } static struct intel_uncore_type bdx_uncore_ha = …; static struct intel_uncore_type bdx_uncore_imc = …; static struct intel_uncore_type bdx_uncore_irp = …; static struct intel_uncore_type bdx_uncore_qpi = …; static struct event_constraint bdx_uncore_r2pcie_constraints[] = …; static struct intel_uncore_type bdx_uncore_r2pcie = …; static struct event_constraint bdx_uncore_r3qpi_constraints[] = …; static struct intel_uncore_type bdx_uncore_r3qpi = …; enum { … }; static struct intel_uncore_type *bdx_pci_uncores[] = …; static const struct pci_device_id bdx_uncore_pci_ids[] = …; static struct pci_driver bdx_uncore_pci_driver = …; int bdx_uncore_pci_init(void) { … } /* end of BDX uncore support */ /* SKX uncore support */ static struct intel_uncore_type skx_uncore_ubox = …; static struct attribute *skx_uncore_cha_formats_attr[] = …; static const struct attribute_group skx_uncore_chabox_format_group = …; static struct event_constraint skx_uncore_chabox_constraints[] = …; static struct extra_reg skx_uncore_cha_extra_regs[] = …; static u64 skx_cha_filter_mask(int fields) { … } static struct event_constraint * skx_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event) { … } static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops skx_uncore_chabox_ops = …; static struct intel_uncore_type skx_uncore_chabox = …; static struct attribute *skx_uncore_iio_formats_attr[] = …; static const struct attribute_group skx_uncore_iio_format_group = …; static struct event_constraint skx_uncore_iio_constraints[] = …; static void skx_iio_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops skx_uncore_iio_ops = …; static struct intel_uncore_topology *pmu_topology(struct intel_uncore_pmu *pmu, int die) { … } static umode_t pmu_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die, int zero_bus_pmu) { … } static umode_t skx_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die) { … } static ssize_t skx_iio_mapping_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static int skx_msr_cpu_bus_read(int cpu, u64 *topology) { … } static int die_to_cpu(int die) { … } enum { … }; static const size_t topology_size[TOPOLOGY_MAX] = …; static int pmu_alloc_topology(struct intel_uncore_type *type, int topology_type) { … } static void pmu_free_topology(struct intel_uncore_type *type) { … } static int skx_pmu_get_topology(struct intel_uncore_type *type, int (*topology_cb)(struct intel_uncore_type*, int, int, u64)) { … } static int skx_iio_topology_cb(struct intel_uncore_type *type, int segment, int die, u64 cpu_bus_msr) { … } static int skx_iio_get_topology(struct intel_uncore_type *type) { … } static struct attribute_group skx_iio_mapping_group = …; static const struct attribute_group *skx_iio_attr_update[] = …; static void pmu_clear_mapping_attr(const struct attribute_group **groups, struct attribute_group *ag) { … } static void pmu_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag, ssize_t (*show)(struct device*, struct device_attribute*, char*), int topology_type) { … } static void pmu_cleanup_mapping(struct intel_uncore_type *type, struct attribute_group *ag) { … } static void pmu_iio_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag) { … } static void skx_iio_set_mapping(struct intel_uncore_type *type) { … } static void skx_iio_cleanup_mapping(struct intel_uncore_type *type) { … } static struct intel_uncore_type skx_uncore_iio = …; enum perf_uncore_iio_freerunning_type_id { … }; static struct freerunning_counters skx_iio_freerunning[] = …; static struct uncore_event_desc skx_uncore_iio_freerunning_events[] = …; static struct intel_uncore_ops skx_uncore_iio_freerunning_ops = …; static struct attribute *skx_uncore_iio_freerunning_formats_attr[] = …; static const struct attribute_group skx_uncore_iio_freerunning_format_group = …; static struct intel_uncore_type skx_uncore_iio_free_running = …; static struct attribute *skx_uncore_formats_attr[] = …; static const struct attribute_group skx_uncore_format_group = …; static struct intel_uncore_type skx_uncore_irp = …; static struct attribute *skx_uncore_pcu_formats_attr[] = …; static struct attribute_group skx_uncore_pcu_format_group = …; static struct intel_uncore_ops skx_uncore_pcu_ops = …; static struct intel_uncore_type skx_uncore_pcu = …; static struct intel_uncore_type *skx_msr_uncores[] = …; /* * To determine the number of CHAs, it should read bits 27:0 in the CAPID6 * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083. */ #define SKX_CAPID6 … #define SKX_CHA_BIT_MASK … static int skx_count_chabox(void) { … } void skx_uncore_cpu_init(void) { … } static struct intel_uncore_type skx_uncore_imc = …; static struct attribute *skx_upi_uncore_formats_attr[] = …; static const struct attribute_group skx_upi_uncore_format_group = …; static void skx_upi_uncore_pci_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops skx_upi_uncore_pci_ops = …; static umode_t skx_upi_mapping_visible(struct kobject *kobj, struct attribute *attr, int die) { … } static ssize_t skx_upi_mapping_show(struct device *dev, struct device_attribute *attr, char *buf) { … } #define SKX_UPI_REG_DID … #define SKX_UPI_REGS_ADDR_DEVICE_LINK0 … #define SKX_UPI_REGS_ADDR_FUNCTION … /* * UPI Link Parameter 0 * | Bit | Default | Description * | 19:16 | 0h | base_nodeid - The NodeID of the sending socket. * | 12:8 | 00h | sending_port - The processor die port number of the sending port. */ #define SKX_KTILP0_OFFSET … /* * UPI Pcode Status. This register is used by PCode to store the link training status. * | Bit | Default | Description * | 4 | 0h | ll_status_valid — Bit indicates the valid training status * logged from PCode to the BIOS. */ #define SKX_KTIPCSTS_OFFSET … static int upi_fill_topology(struct pci_dev *dev, struct intel_uncore_topology *tp, int pmu_idx) { … } static int skx_upi_topology_cb(struct intel_uncore_type *type, int segment, int die, u64 cpu_bus_msr) { … } static int skx_upi_get_topology(struct intel_uncore_type *type) { … } static struct attribute_group skx_upi_mapping_group = …; static const struct attribute_group *skx_upi_attr_update[] = …; static void pmu_upi_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag) { … } static void skx_upi_set_mapping(struct intel_uncore_type *type) { … } static void skx_upi_cleanup_mapping(struct intel_uncore_type *type) { … } static struct intel_uncore_type skx_uncore_upi = …; static void skx_m2m_uncore_pci_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops skx_m2m_uncore_pci_ops = …; static struct intel_uncore_type skx_uncore_m2m = …; static struct event_constraint skx_uncore_m2pcie_constraints[] = …; static struct intel_uncore_type skx_uncore_m2pcie = …; static struct event_constraint skx_uncore_m3upi_constraints[] = …; static struct intel_uncore_type skx_uncore_m3upi = …; enum { … }; static struct intel_uncore_type *skx_pci_uncores[] = …; static const struct pci_device_id skx_uncore_pci_ids[] = …; static struct pci_driver skx_uncore_pci_driver = …; int skx_uncore_pci_init(void) { … } /* end of SKX uncore support */ /* SNR uncore support */ static struct intel_uncore_type snr_uncore_ubox = …; static struct attribute *snr_uncore_cha_formats_attr[] = …; static const struct attribute_group snr_uncore_chabox_format_group = …; static int snr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static void snr_cha_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops snr_uncore_chabox_ops = …; static struct intel_uncore_type snr_uncore_chabox = …; static struct attribute *snr_uncore_iio_formats_attr[] = …; static const struct attribute_group snr_uncore_iio_format_group = …; static umode_t snr_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die) { … } static struct attribute_group snr_iio_mapping_group = …; static const struct attribute_group *snr_iio_attr_update[] = …; static int sad_cfg_iio_topology(struct intel_uncore_type *type, u8 *sad_pmon_mapping) { … } /* * SNR has a static mapping of stack IDs from SAD_CONTROL_CFG notation to PMON */ enum { … }; static u8 snr_sad_pmon_mapping[] = …; static int snr_iio_get_topology(struct intel_uncore_type *type) { … } static void snr_iio_set_mapping(struct intel_uncore_type *type) { … } static void snr_iio_cleanup_mapping(struct intel_uncore_type *type) { … } static struct event_constraint snr_uncore_iio_constraints[] = …; static struct intel_uncore_type snr_uncore_iio = …; static struct intel_uncore_type snr_uncore_irp = …; static struct intel_uncore_type snr_uncore_m2pcie = …; static int snr_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops snr_uncore_pcu_ops = …; static struct intel_uncore_type snr_uncore_pcu = …; enum perf_uncore_snr_iio_freerunning_type_id { … }; static struct freerunning_counters snr_iio_freerunning[] = …; static struct uncore_event_desc snr_uncore_iio_freerunning_events[] = …; static struct intel_uncore_type snr_uncore_iio_free_running = …; static struct intel_uncore_type *snr_msr_uncores[] = …; void snr_uncore_cpu_init(void) { … } static void snr_m2m_uncore_pci_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops snr_m2m_uncore_pci_ops = …; static struct attribute *snr_m2m_uncore_formats_attr[] = …; static const struct attribute_group snr_m2m_uncore_format_group = …; static struct intel_uncore_type snr_uncore_m2m = …; static void snr_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops snr_pcie3_uncore_pci_ops = …; static struct intel_uncore_type snr_uncore_pcie3 = …; enum { … }; static struct intel_uncore_type *snr_pci_uncores[] = …; static const struct pci_device_id snr_uncore_pci_ids[] = …; static struct pci_driver snr_uncore_pci_driver = …; static const struct pci_device_id snr_uncore_pci_sub_ids[] = …; static struct pci_driver snr_uncore_pci_sub_driver = …; int snr_uncore_pci_init(void) { … } #define SNR_MC_DEVICE_ID … static struct pci_dev *snr_uncore_get_mc_dev(unsigned int device, int id) { … } static int snr_uncore_mmio_map(struct intel_uncore_box *box, unsigned int box_ctl, int mem_offset, unsigned int device) { … } static void __snr_uncore_mmio_init_box(struct intel_uncore_box *box, unsigned int box_ctl, int mem_offset, unsigned int device) { … } static void snr_uncore_mmio_init_box(struct intel_uncore_box *box) { … } static void snr_uncore_mmio_disable_box(struct intel_uncore_box *box) { … } static void snr_uncore_mmio_enable_box(struct intel_uncore_box *box) { … } static void snr_uncore_mmio_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void snr_uncore_mmio_disable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops snr_uncore_mmio_ops = …; static struct uncore_event_desc snr_uncore_imc_events[] = …; static struct intel_uncore_type snr_uncore_imc = …; enum perf_uncore_snr_imc_freerunning_type_id { … }; static struct freerunning_counters snr_imc_freerunning[] = …; static struct uncore_event_desc snr_uncore_imc_freerunning_events[] = …; static struct intel_uncore_ops snr_uncore_imc_freerunning_ops = …; static struct intel_uncore_type snr_uncore_imc_free_running = …; static struct intel_uncore_type *snr_mmio_uncores[] = …; void snr_uncore_mmio_init(void) { … } /* end of SNR uncore support */ /* ICX uncore support */ static u64 icx_cha_msr_offsets[] = …; static int icx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops icx_uncore_chabox_ops = …; static struct intel_uncore_type icx_uncore_chabox = …; static u64 icx_msr_offsets[] = …; static struct event_constraint icx_uncore_iio_constraints[] = …; static umode_t icx_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die) { … } static struct attribute_group icx_iio_mapping_group = …; static const struct attribute_group *icx_iio_attr_update[] = …; /* * ICX has a static mapping of stack IDs from SAD_CONTROL_CFG notation to PMON */ enum { … }; static u8 icx_sad_pmon_mapping[] = …; static int icx_iio_get_topology(struct intel_uncore_type *type) { … } static void icx_iio_set_mapping(struct intel_uncore_type *type) { … } static void icx_iio_cleanup_mapping(struct intel_uncore_type *type) { … } static struct intel_uncore_type icx_uncore_iio = …; static struct intel_uncore_type icx_uncore_irp = …; static struct event_constraint icx_uncore_m2pcie_constraints[] = …; static struct intel_uncore_type icx_uncore_m2pcie = …; enum perf_uncore_icx_iio_freerunning_type_id { … }; static unsigned icx_iio_clk_freerunning_box_offsets[] = …; static unsigned icx_iio_bw_freerunning_box_offsets[] = …; static struct freerunning_counters icx_iio_freerunning[] = …; static struct uncore_event_desc icx_uncore_iio_freerunning_events[] = …; static struct intel_uncore_type icx_uncore_iio_free_running = …; static struct intel_uncore_type *icx_msr_uncores[] = …; /* * To determine the number of CHAs, it should read CAPID6(Low) and CAPID7 (High) * registers which located at Device 30, Function 3 */ #define ICX_CAPID6 … #define ICX_CAPID7 … static u64 icx_count_chabox(void) { … } void icx_uncore_cpu_init(void) { … } static struct intel_uncore_type icx_uncore_m2m = …; static struct attribute *icx_upi_uncore_formats_attr[] = …; static const struct attribute_group icx_upi_uncore_format_group = …; #define ICX_UPI_REGS_ADDR_DEVICE_LINK0 … #define ICX_UPI_REGS_ADDR_FUNCTION … static int discover_upi_topology(struct intel_uncore_type *type, int ubox_did, int dev_link0) { … } static int icx_upi_get_topology(struct intel_uncore_type *type) { … } static struct attribute_group icx_upi_mapping_group = …; static const struct attribute_group *icx_upi_attr_update[] = …; static void icx_upi_set_mapping(struct intel_uncore_type *type) { … } static void icx_upi_cleanup_mapping(struct intel_uncore_type *type) { … } static struct intel_uncore_type icx_uncore_upi = …; static struct event_constraint icx_uncore_m3upi_constraints[] = …; static struct intel_uncore_type icx_uncore_m3upi = …; enum { … }; static struct intel_uncore_type *icx_pci_uncores[] = …; static const struct pci_device_id icx_uncore_pci_ids[] = …; static struct pci_driver icx_uncore_pci_driver = …; int icx_uncore_pci_init(void) { … } static void icx_uncore_imc_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops icx_uncore_mmio_ops = …; static struct intel_uncore_type icx_uncore_imc = …; enum perf_uncore_icx_imc_freerunning_type_id { … }; static struct freerunning_counters icx_imc_freerunning[] = …; static struct uncore_event_desc icx_uncore_imc_freerunning_events[] = …; static void icx_uncore_imc_freerunning_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops icx_uncore_imc_freerunning_ops = …; static struct intel_uncore_type icx_uncore_imc_free_running = …; static struct intel_uncore_type *icx_mmio_uncores[] = …; void icx_uncore_mmio_init(void) { … } /* end of ICX uncore support */ /* SPR uncore support */ static void spr_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static void spr_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static int spr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops spr_uncore_chabox_ops = …; static struct attribute *spr_uncore_cha_formats_attr[] = …; static const struct attribute_group spr_uncore_chabox_format_group = …; static ssize_t alias_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static DEVICE_ATTR_RO(alias); static struct attribute *uncore_alias_attrs[] = …; ATTRIBUTE_GROUPS(…); static struct intel_uncore_type spr_uncore_chabox = …; static struct intel_uncore_type spr_uncore_iio = …; static struct attribute *spr_uncore_raw_formats_attr[] = …; static const struct attribute_group spr_uncore_raw_format_group = …; #define SPR_UNCORE_COMMON_FORMAT() … static struct intel_uncore_type spr_uncore_irp = …; static struct event_constraint spr_uncore_m2pcie_constraints[] = …; static struct intel_uncore_type spr_uncore_m2pcie = …; static struct intel_uncore_type spr_uncore_pcu = …; static void spr_uncore_mmio_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops spr_uncore_mmio_ops = …; static struct uncore_event_desc spr_uncore_imc_events[] = …; #define SPR_UNCORE_MMIO_COMMON_FORMAT() … static struct intel_uncore_type spr_uncore_imc = …; static void spr_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event) { … } static struct intel_uncore_ops spr_uncore_pci_ops = …; #define SPR_UNCORE_PCI_COMMON_FORMAT() … static struct intel_uncore_type spr_uncore_m2m = …; static struct attribute_group spr_upi_mapping_group = …; static const struct attribute_group *spr_upi_attr_update[] = …; #define SPR_UPI_REGS_ADDR_DEVICE_LINK0 … static void spr_upi_set_mapping(struct intel_uncore_type *type) { … } static void spr_upi_cleanup_mapping(struct intel_uncore_type *type) { … } static int spr_upi_get_topology(struct intel_uncore_type *type) { … } static struct intel_uncore_type spr_uncore_mdf = …; static void spr_uncore_mmio_offs8_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops spr_uncore_mmio_offs8_ops = …; #define SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT() … static struct event_constraint spr_uncore_cxlcm_constraints[] = …; static struct intel_uncore_type spr_uncore_cxlcm = …; static struct intel_uncore_type spr_uncore_cxldp = …; static struct intel_uncore_type spr_uncore_hbm = …; #define UNCORE_SPR_NUM_UNCORE_TYPES … #define UNCORE_SPR_CHA … #define UNCORE_SPR_IIO … #define UNCORE_SPR_IMC … #define UNCORE_SPR_UPI … #define UNCORE_SPR_M3UPI … /* * The uncore units, which are supported by the discovery table, * are defined here. */ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = …; /* * The uncore units, which are not supported by the discovery table, * are implemented from here. */ #define SPR_UNCORE_UPI_NUM_BOXES … static u64 spr_upi_pci_offsets[SPR_UNCORE_UPI_NUM_BOXES] = …; static void spr_extra_boxes_cleanup(struct intel_uncore_type *type) { … } static struct intel_uncore_type spr_uncore_upi = …; static struct intel_uncore_type spr_uncore_m3upi = …; enum perf_uncore_spr_iio_freerunning_type_id { … }; static struct freerunning_counters spr_iio_freerunning[] = …; static struct uncore_event_desc spr_uncore_iio_freerunning_events[] = …; static struct intel_uncore_type spr_uncore_iio_free_running = …; enum perf_uncore_spr_imc_freerunning_type_id { … }; static struct freerunning_counters spr_imc_freerunning[] = …; static struct uncore_event_desc spr_uncore_imc_freerunning_events[] = …; #define SPR_MC_DEVICE_ID … static void spr_uncore_imc_freerunning_init_box(struct intel_uncore_box *box) { … } static struct intel_uncore_ops spr_uncore_imc_freerunning_ops = …; static struct intel_uncore_type spr_uncore_imc_free_running = …; #define UNCORE_SPR_MSR_EXTRA_UNCORES … #define UNCORE_SPR_MMIO_EXTRA_UNCORES … #define UNCORE_SPR_PCI_EXTRA_UNCORES … static struct intel_uncore_type *spr_msr_uncores[UNCORE_SPR_MSR_EXTRA_UNCORES] = …; static struct intel_uncore_type *spr_mmio_uncores[UNCORE_SPR_MMIO_EXTRA_UNCORES] = …; static struct intel_uncore_type *spr_pci_uncores[UNCORE_SPR_PCI_EXTRA_UNCORES] = …; int spr_uncore_units_ignore[] = …; static void uncore_type_customized_copy(struct intel_uncore_type *to_type, struct intel_uncore_type *from_type) { … } static struct intel_uncore_type ** uncore_get_uncores(enum uncore_access_type type_id, int num_extra, struct intel_uncore_type **extra, int max_num_types, struct intel_uncore_type **uncores) { … } static struct intel_uncore_type * uncore_find_type_by_id(struct intel_uncore_type **types, int type_id) { … } static int uncore_type_max_boxes(struct intel_uncore_type **types, int type_id) { … } #define SPR_MSR_UNC_CBO_CONFIG … void spr_uncore_cpu_init(void) { … } #define SPR_UNCORE_UPI_PCIID … #define SPR_UNCORE_UPI0_DEVFN … #define SPR_UNCORE_M3UPI_PCIID … #define SPR_UNCORE_M3UPI0_DEVFN … static void spr_update_device_location(int type_id) { … } int spr_uncore_pci_init(void) { … } void spr_uncore_mmio_init(void) { … } /* end of SPR uncore support */ /* GNR uncore support */ #define UNCORE_GNR_NUM_UNCORE_TYPES … #define UNCORE_GNR_TYPE_15 … #define UNCORE_GNR_B2UPI … #define UNCORE_GNR_TYPE_21 … #define UNCORE_GNR_TYPE_22 … int gnr_uncore_units_ignore[] = …; static struct intel_uncore_type gnr_uncore_ubox = …; static struct intel_uncore_type gnr_uncore_b2cmi = …; static struct intel_uncore_type gnr_uncore_b2cxl = …; static struct intel_uncore_type gnr_uncore_mdf_sbo = …; static struct intel_uncore_type *gnr_uncores[UNCORE_GNR_NUM_UNCORE_TYPES] = …; static struct freerunning_counters gnr_iio_freerunning[] = …; void gnr_uncore_cpu_init(void) { … } int gnr_uncore_pci_init(void) { … } void gnr_uncore_mmio_init(void) { … } /* end of GNR uncore support */
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