// SPDX-License-Identifier: GPL-2.0 /* * Cortina Gemini SoC Clock Controller driver * Copyright (c) 2017 Linus Walleij <[email protected]> */ #define pr_fmt(fmt) … #include <linux/init.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/io.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/spinlock.h> #include <linux/reset-controller.h> #include <dt-bindings/reset/cortina,gemini-reset.h> #include <dt-bindings/clock/cortina,gemini-clock.h> /* Globally visible clocks */ static DEFINE_SPINLOCK(gemini_clk_lock); #define GEMINI_GLOBAL_STATUS … #define PLL_OSC_SEL … #define AHBSPEED_SHIFT … #define AHBSPEED_MASK … #define CPU_AHB_RATIO_SHIFT … #define CPU_AHB_RATIO_MASK … #define GEMINI_GLOBAL_PLL_CONTROL … #define GEMINI_GLOBAL_SOFT_RESET … #define GEMINI_GLOBAL_MISC_CONTROL … #define PCI_CLK_66MHZ … #define GEMINI_GLOBAL_CLOCK_CONTROL … #define PCI_CLKRUN_EN … #define TVC_HALFDIV_SHIFT … #define TVC_HALFDIV_MASK … #define SECURITY_CLK_SEL … #define GEMINI_GLOBAL_PCI_DLL_CONTROL … #define PCI_DLL_BYPASS … #define PCI_DLL_TAP_SEL_MASK … /** * struct gemini_gate_data - Gemini gated clocks * @bit_idx: the bit used to gate this clock in the clock register * @name: the clock name * @parent_name: the name of the parent clock * @flags: standard clock framework flags */ struct gemini_gate_data { … }; /** * struct clk_gemini_pci - Gemini PCI clock * @hw: corresponding clock hardware entry * @map: regmap to access the registers */ struct clk_gemini_pci { … }; /** * struct gemini_reset - gemini reset controller * @map: regmap to access the containing system controller * @rcdev: reset controller device */ struct gemini_reset { … }; /* Keeps track of all clocks */ static struct clk_hw_onecell_data *gemini_clk_data; static const struct gemini_gate_data gemini_gates[] = …; #define to_pciclk(_hw) … #define to_gemini_reset(p) … static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int gemini_pci_enable(struct clk_hw *hw) { … } static void gemini_pci_disable(struct clk_hw *hw) { … } static int gemini_pci_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops gemini_pci_clk_ops = …; static struct clk_hw *gemini_pci_clk_setup(const char *name, const char *parent_name, struct regmap *map) { … } /* * This is a self-deasserting reset controller. */ static int gemini_reset(struct reset_controller_dev *rcdev, unsigned long id) { … } static int gemini_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int gemini_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int gemini_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { … } static const struct reset_control_ops gemini_reset_ops = …; static int gemini_clk_probe(struct platform_device *pdev) { … } static const struct of_device_id gemini_clk_dt_ids[] = …; static struct platform_driver gemini_clk_driver = …; builtin_platform_driver(…) …; static void __init gemini_cc_init(struct device_node *np) { … } CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
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