/* SPDX-License-Identifier: GPL-2.0-only */ /* * AMD Passthru DMA device driver * -- Based on the CCP driver * * Copyright (C) 2016,2021 Advanced Micro Devices, Inc. * * Author: Sanjay R Mehta <[email protected]> * Author: Tom Lendacky <[email protected]> * Author: Gary R Hook <[email protected]> */ #ifndef __PT_DEV_H__ #define __PT_DEV_H__ #include <linux/device.h> #include <linux/dmaengine.h> #include <linux/pci.h> #include <linux/spinlock.h> #include <linux/mutex.h> #include <linux/list.h> #include <linux/wait.h> #include <linux/dmapool.h> #include "../virt-dma.h" #define MAX_PT_NAME_LEN … #define MAX_DMAPOOL_NAME_LEN … #define MAX_HW_QUEUES … #define MAX_CMD_QLEN … #define PT_ENGINE_PASSTHRU … /* Register Mappings */ #define IRQ_MASK_REG … #define IRQ_STATUS_REG … #define CMD_Q_ERROR(__qs) … #define CMD_QUEUE_PRIO_OFFSET … #define CMD_REQID_CONFIG_OFFSET … #define CMD_TIMEOUT_OFFSET … #define CMD_PT_VERSION … #define CMD_Q_CONTROL_BASE … #define CMD_Q_TAIL_LO_BASE … #define CMD_Q_HEAD_LO_BASE … #define CMD_Q_INT_ENABLE_BASE … #define CMD_Q_INTERRUPT_STATUS_BASE … #define CMD_Q_STATUS_BASE … #define CMD_Q_INT_STATUS_BASE … #define CMD_Q_DMA_STATUS_BASE … #define CMD_Q_DMA_READ_STATUS_BASE … #define CMD_Q_DMA_WRITE_STATUS_BASE … #define CMD_Q_ABORT_BASE … #define CMD_Q_AX_CACHE_BASE … #define CMD_CONFIG_OFFSET … #define CMD_CLK_GATE_CTL_OFFSET … #define CMD_DESC_DW0_VAL … /* Address offset for virtual queue registers */ #define CMD_Q_STATUS_INCR … /* Bit masks */ #define CMD_CONFIG_REQID … #define CMD_TIMEOUT_DISABLE … #define CMD_CLK_DYN_GATING_DIS … #define CMD_CLK_SW_GATE_MODE … #define CMD_CLK_GATE_CTL … #define CMD_QUEUE_PRIO … #define CMD_CONFIG_VHB_EN … #define CMD_CLK_DYN_GATING_EN … #define CMD_CLK_HW_GATE_MODE … #define CMD_CLK_GATE_ON_DELAY … #define CMD_CLK_GATE_OFF_DELAY … #define CMD_CLK_GATE_CONFIG … #define CMD_Q_LEN … #define CMD_Q_RUN … #define CMD_Q_HALT … #define CMD_Q_MEM_LOCATION … #define CMD_Q_SIZE_MASK … #define CMD_Q_SIZE … #define CMD_Q_SHIFT … #define QUEUE_SIZE_VAL … #define Q_PTR_MASK … #define Q_DESC_SIZE … #define Q_SIZE(n) … #define INT_COMPLETION … #define INT_ERROR … #define INT_QUEUE_STOPPED … #define INT_EMPTY_QUEUE … #define SUPPORTED_INTERRUPTS … /****** Local Storage Block ******/ #define LSB_START … #define LSB_END … #define LSB_COUNT … #define PT_DMAPOOL_MAX_SIZE … #define PT_DMAPOOL_ALIGN … #define PT_PASSTHRU_BLOCKSIZE … struct pt_device; struct pt_tasklet_data { … }; /* * struct pt_passthru_engine - pass-through operation * without performing DMA mapping * @mask: mask to be applied to data * @mask_len: length in bytes of mask * @src_dma: data to be used for this operation * @dst_dma: data produced by this operation * @src_len: length in bytes of data used for this operation * * Variables required to be set when calling pt_enqueue_cmd(): * - bit_mod, byte_swap, src, dst, src_len * - mask, mask_len if bit_mod is not PT_PASSTHRU_BITWISE_NOOP */ struct pt_passthru_engine { … }; /* * struct pt_cmd - PTDMA operation request * @entry: list element * @work: work element used for callbacks * @pt: PT device to be run on * @ret: operation return code * @flags: cmd processing flags * @engine: PTDMA operation to perform (passthru) * @engine_error: PT engine return code * @passthru: engine specific structures, refer to specific engine struct below * @callback: operation completion callback function * @data: parameter value to be supplied to the callback function * * Variables required to be set when calling pt_enqueue_cmd(): * - engine, callback * - See the operation structures below for what is required for each * operation. */ struct pt_cmd { … }; struct pt_dma_desc { … }; struct pt_dma_chan { … }; struct pt_cmd_queue { … } ____cacheline_aligned; struct pt_device { … }; /* * descriptor for PTDMA commands * 8 32-bit words: * word 0: function; engine; control bits * word 1: length of source data * word 2: low 32 bits of source pointer * word 3: upper 16 bits of source pointer; source memory type * word 4: low 32 bits of destination pointer * word 5: upper 16 bits of destination pointer; destination memory type * word 6: reserved 32 bits * word 7: reserved 32 bits */ #define DWORD0_SOC … #define DWORD0_IOC … struct dword3 { … }; struct dword5 { … }; struct ptdma_desc { … }; /* Structure to hold PT device data */ struct pt_dev_vdata { … }; int pt_dmaengine_register(struct pt_device *pt); void pt_dmaengine_unregister(struct pt_device *pt); void ptdma_debugfs_setup(struct pt_device *pt); int pt_core_init(struct pt_device *pt); void pt_core_destroy(struct pt_device *pt); int pt_core_perform_passthru(struct pt_cmd_queue *cmd_q, struct pt_passthru_engine *pt_engine); void pt_check_status_trans(struct pt_device *pt, struct pt_cmd_queue *cmd_q); void pt_start_queue(struct pt_cmd_queue *cmd_q); void pt_stop_queue(struct pt_cmd_queue *cmd_q); static inline void pt_core_disable_queue_interrupts(struct pt_device *pt) { … } static inline void pt_core_enable_queue_interrupts(struct pt_device *pt) { … } #endif
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