/* SPDX-License-Identifier: GPL-2.0 */ /* * Driver for the Synopsys DesignWare AHB DMA Controller * * Copyright (C) 2005-2007 Atmel Corporation * Copyright (C) 2010-2011 ST Microelectronics * Copyright (C) 2016 Intel Corporation */ #include <linux/bitops.h> #include <linux/interrupt.h> #include <linux/dmaengine.h> #include <linux/io-64-nonatomic-hi-lo.h> #include "internal.h" #define DW_DMA_MAX_NR_REQUESTS … /* flow controller */ enum dw_dma_fc { … }; /* * Redefine this macro to handle differences between 32- and 64-bit * addressing, big vs. little endian, etc. */ #define DW_REG(name) … /* Hardware register definitions. */ struct dw_dma_chan_regs { … }; struct dw_dma_irq_regs { … }; struct dw_dma_regs { … }; /* Bitfields in DW_PARAMS */ #define DW_PARAMS_NR_CHAN … #define DW_PARAMS_NR_MASTER … #define DW_PARAMS_DATA_WIDTH(n) … #define DW_PARAMS_DATA_WIDTH1 … #define DW_PARAMS_DATA_WIDTH2 … #define DW_PARAMS_DATA_WIDTH3 … #define DW_PARAMS_DATA_WIDTH4 … #define DW_PARAMS_EN … /* Bitfields in DWC_PARAMS */ #define DWC_PARAMS_MBLK_EN … #define DWC_PARAMS_HC_LLP … #define DWC_PARAMS_MSIZE … /* bursts size */ enum dw_dma_msize { … }; /* Bitfields in LLP */ #define DWC_LLP_LMS(x) … #define DWC_LLP_LOC(x) … /* Bitfields in CTL_LO */ #define DWC_CTLL_INT_EN … #define DWC_CTLL_DST_WIDTH(n) … #define DWC_CTLL_SRC_WIDTH(n) … #define DWC_CTLL_DST_INC … #define DWC_CTLL_DST_DEC … #define DWC_CTLL_DST_FIX … #define DWC_CTLL_SRC_INC … #define DWC_CTLL_SRC_DEC … #define DWC_CTLL_SRC_FIX … #define DWC_CTLL_DST_MSIZE(n) … #define DWC_CTLL_SRC_MSIZE(n) … #define DWC_CTLL_S_GATH_EN … #define DWC_CTLL_D_SCAT_EN … #define DWC_CTLL_FC(n) … #define DWC_CTLL_FC_M2M … #define DWC_CTLL_FC_M2P … #define DWC_CTLL_FC_P2M … #define DWC_CTLL_FC_P2P … /* plus 4 transfer types for peripheral-as-flow-controller */ #define DWC_CTLL_DMS(n) … #define DWC_CTLL_SMS(n) … #define DWC_CTLL_LLP_D_EN … #define DWC_CTLL_LLP_S_EN … /* Bitfields in CTL_HI */ #define DWC_CTLH_BLOCK_TS_MASK … #define DWC_CTLH_BLOCK_TS(x) … #define DWC_CTLH_DONE … /* Bitfields in CFG_LO */ #define DWC_CFGL_CH_PRIOR_MASK … #define DWC_CFGL_CH_PRIOR(x) … #define DWC_CFGL_CH_SUSP … #define DWC_CFGL_FIFO_EMPTY … #define DWC_CFGL_HS_DST … #define DWC_CFGL_HS_SRC … #define DWC_CFGL_LOCK_CH_XFER … #define DWC_CFGL_LOCK_CH_BLOCK … #define DWC_CFGL_LOCK_CH_XACT … #define DWC_CFGL_LOCK_BUS_XFER … #define DWC_CFGL_LOCK_BUS_BLOCK … #define DWC_CFGL_LOCK_BUS_XACT … #define DWC_CFGL_LOCK_CH … #define DWC_CFGL_LOCK_BUS … #define DWC_CFGL_HS_DST_POL … #define DWC_CFGL_HS_SRC_POL … #define DWC_CFGL_MAX_BURST(x) … #define DWC_CFGL_RELOAD_SAR … #define DWC_CFGL_RELOAD_DAR … /* Bitfields in CFG_HI */ #define DWC_CFGH_FCMODE … #define DWC_CFGH_FIFO_MODE … #define DWC_CFGH_PROTCTL(x) … #define DWC_CFGH_PROTCTL_DATA … #define DWC_CFGH_PROTCTL_PRIV … #define DWC_CFGH_PROTCTL_BUFFER … #define DWC_CFGH_PROTCTL_CACHE … #define DWC_CFGH_DS_UPD_EN … #define DWC_CFGH_SS_UPD_EN … #define DWC_CFGH_SRC_PER(x) … #define DWC_CFGH_DST_PER(x) … /* Bitfields in SGR */ #define DWC_SGR_SGI(x) … #define DWC_SGR_SGC(x) … /* Bitfields in DSR */ #define DWC_DSR_DSI(x) … #define DWC_DSR_DSC(x) … /* Bitfields in CFG */ #define DW_CFG_DMA_EN … /* iDMA 32-bit support */ /* bursts size */ enum idma32_msize { … }; /* Bitfields in CTL_HI */ #define IDMA32C_CTLH_BLOCK_TS_MASK … #define IDMA32C_CTLH_BLOCK_TS(x) … #define IDMA32C_CTLH_DONE … /* Bitfields in CFG_LO */ #define IDMA32C_CFGL_DST_BURST_ALIGN … #define IDMA32C_CFGL_SRC_BURST_ALIGN … #define IDMA32C_CFGL_CH_DRAIN … #define IDMA32C_CFGL_DST_OPT_BL … #define IDMA32C_CFGL_SRC_OPT_BL … /* Bitfields in CFG_HI */ #define IDMA32C_CFGH_SRC_PER(x) … #define IDMA32C_CFGH_DST_PER(x) … #define IDMA32C_CFGH_RD_ISSUE_THD(x) … #define IDMA32C_CFGH_RW_ISSUE_THD(x) … #define IDMA32C_CFGH_SRC_PER_EXT(x) … #define IDMA32C_CFGH_DST_PER_EXT(x) … /* Bitfields in FIFO_PARTITION */ #define IDMA32C_FP_PSIZE_CH0(x) … #define IDMA32C_FP_PSIZE_CH1(x) … #define IDMA32C_FP_UPDATE … enum dw_dmac_flags { … }; struct dw_dma_chan { … }; static inline struct dw_dma_chan_regs __iomem * __dwc_regs(struct dw_dma_chan *dwc) { … } #define channel_readl(dwc, name) … #define channel_writel(dwc, name, val) … static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) { … } struct dw_dma { … }; static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) { … } #define dma_readl(dw, name) … #define dma_writel(dw, name, val) … #define idma32_readq(dw, name) … #define idma32_writeq(dw, name, val) … #define channel_set_bit(dw, reg, mask) … #define channel_clear_bit(dw, reg, mask) … static inline struct dw_dma *to_dw_dma(struct dma_device *ddev) { … } /* LLI == Linked List Item; a.k.a. DMA block descriptor */ struct dw_lli { … }; struct dw_desc { … }; #define to_dw_desc(h) … static inline struct dw_desc * txd_to_dw_desc(struct dma_async_tx_descriptor *txd) { … }
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