linux/drivers/dma/dw-edma/dw-edma-v0-core.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
 * Synopsys DesignWare eDMA v0 core
 *
 * Author: Gustavo Pimentel <[email protected]>
 */

#include <linux/bitfield.h>
#include <linux/irqreturn.h>
#include <linux/io-64-nonatomic-lo-hi.h>

#include "dw-edma-core.h"
#include "dw-edma-v0-core.h"
#include "dw-edma-v0-regs.h"
#include "dw-edma-v0-debugfs.h"

enum dw_edma_control { … };

static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
{ … }

#define SET_32(dw, name, value) …

#define GET_32(dw, name) …

#define SET_RW_32(dw, dir, name, value) …

#define GET_RW_32(dw, dir, name) …

#define SET_BOTH_32(dw, name, value) …

#define SET_64(dw, name, value) …

#define GET_64(dw, name) …

#define SET_RW_64(dw, dir, name, value) …

#define GET_RW_64(dw, dir, name) …

#define SET_BOTH_64(dw, name, value) …

#define SET_COMPAT(dw, name, value) …

#define SET_RW_COMPAT(dw, dir, name, value) …

static inline struct dw_edma_v0_ch_regs __iomem *
__dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch)
{ … }

static inline void writel_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
			     u32 value, void __iomem *addr)
{ … }

static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
			   const void __iomem *addr)
{ … }

#define SET_CH_32(dw, dir, ch, name, value) …

#define GET_CH_32(dw, dir, ch, name) …

/* eDMA management callbacks */
static void dw_edma_v0_core_off(struct dw_edma *dw)
{ … }

static u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
{ … }

static enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan)
{ … }

static void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan)
{ … }

static void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan)
{ … }

static u32 dw_edma_v0_core_status_done_int(struct dw_edma *dw, enum dw_edma_dir dir)
{ … }

static u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir)
{ … }

static irqreturn_t
dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir,
			   dw_edma_handler_t done, dw_edma_handler_t abort)
{ … }

static void dw_edma_v0_write_ll_data(struct dw_edma_chunk *chunk, int i,
				     u32 control, u32 size, u64 sar, u64 dar)
{ … }

static void dw_edma_v0_write_ll_link(struct dw_edma_chunk *chunk,
				     int i, u32 control, u64 pointer)
{ … }

static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
{ … }

static void dw_edma_v0_sync_ll_data(struct dw_edma_chunk *chunk)
{ … }

static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
{ … }

static void dw_edma_v0_core_ch_config(struct dw_edma_chan *chan)
{ … }

/* eDMA debugfs callbacks */
static void dw_edma_v0_core_debugfs_on(struct dw_edma *dw)
{ … }

static const struct dw_edma_core_ops dw_edma_v0_core = …;

void dw_edma_v0_core_register(struct dw_edma *dw)
{ … }