linux/drivers/dma/hsu/hsu.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Driver for the High Speed UART DMA
 *
 * Copyright (C) 2015 Intel Corporation
 *
 * Partially based on the bits found in drivers/tty/serial/mfd.c.
 */

#ifndef __DMA_HSU_H__
#define __DMA_HSU_H__

#include <linux/bits.h>
#include <linux/container_of.h>
#include <linux/io.h>
#include <linux/types.h>

#include <linux/dma/hsu.h>

#include "../virt-dma.h"

#define HSU_CH_SR …
#define HSU_CH_CR …
#define HSU_CH_DCR …
#define HSU_CH_BSR …
#define HSU_CH_MTSR …
#define HSU_CH_DxSAR(x) …
#define HSU_CH_DxTSR(x) …
#define HSU_CH_D0SAR …
#define HSU_CH_D0TSR …
#define HSU_CH_D1SAR …
#define HSU_CH_D1TSR …
#define HSU_CH_D2SAR …
#define HSU_CH_D2TSR …
#define HSU_CH_D3SAR …
#define HSU_CH_D3TSR …

#define HSU_DMA_CHAN_NR_DESC …
#define HSU_DMA_CHAN_LENGTH …

/* Bits in HSU_CH_SR */
#define HSU_CH_SR_DESCTO(x) …
#define HSU_CH_SR_DESCTO_ANY …
#define HSU_CH_SR_CHE …
#define HSU_CH_SR_DESCE(x) …
#define HSU_CH_SR_DESCE_ANY …
#define HSU_CH_SR_CDESC_ANY …

/* Bits in HSU_CH_CR */
#define HSU_CH_CR_CHA …
#define HSU_CH_CR_CHD …

/* Bits in HSU_CH_DCR */
#define HSU_CH_DCR_DESCA(x) …
#define HSU_CH_DCR_CHSOD(x) …
#define HSU_CH_DCR_CHSOTO …
#define HSU_CH_DCR_CHSOE …
#define HSU_CH_DCR_CHDI(x) …
#define HSU_CH_DCR_CHEI …
#define HSU_CH_DCR_CHTOI(x) …

/* Bits in HSU_CH_DxTSR */
#define HSU_CH_DxTSR_MASK …
#define HSU_CH_DxTSR_TSR(x) …

struct hsu_dma_sg { … };

struct hsu_dma_desc { … };

static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc)
{ … }

struct hsu_dma_chan { … };

static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan)
{ … }

static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset)
{ … }

static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset,
				   u32 value)
{ … }

struct hsu_dma { … };

static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev)
{ … }

#endif /* __DMA_HSU_H__ */