// SPDX-License-Identifier: GPL-2.0+ /* * Renesas SuperH DMA Engine support * * base is drivers/dma/flsdma.c * * Copyright (C) 2011-2012 Guennadi Liakhovetski <[email protected]> * Copyright (C) 2009 Nobuhiro Iwamatsu <[email protected]> * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * * - DMA of SuperH does not have Hardware DMA chain mode. * - MAX DMA size is 16MB. * */ #include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/err.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/kdebug.h> #include <linux/module.h> #include <linux/notifier.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/rculist.h> #include <linux/sh_dma.h> #include <linux/slab.h> #include <linux/spinlock.h> #include "../dmaengine.h" #include "shdma.h" /* DMA registers */ #define SAR … #define DAR … #define TCR … #define CHCR … #define DMAOR … #define TEND … #define SH_DMAE_DRV_NAME … /* Default MEMCPY transfer size = 2^2 = 4 bytes */ #define LOG2_DEFAULT_XFER_SIZE … #define SH_DMA_SLAVE_NUMBER … #define SH_DMA_TCR_MAX … /* * Used for write-side mutual exclusion for the global device list, * read-side synchronization by way of RCU, and per-controller data. */ static DEFINE_SPINLOCK(sh_dmae_lock); static LIST_HEAD(sh_dmae_devices); /* * Different DMAC implementations provide different ways to clear DMA channels: * (1) none - no CHCLR registers are available * (2) one CHCLR register per channel - 0 has to be written to it to clear * channel buffers * (3) one CHCLR per several channels - 1 has to be written to the bit, * corresponding to the specific channel to reset it */ static void channel_clear(struct sh_dmae_chan *sh_dc) { … } static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) { … } static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) { … } static u16 dmaor_read(struct sh_dmae_device *shdev) { … } static void dmaor_write(struct sh_dmae_device *shdev, u16 data) { … } static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data) { … } static u32 chcr_read(struct sh_dmae_chan *sh_dc) { … } /* * Reset DMA controller * * SH7780 has two DMAOR register */ static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) { … } static int sh_dmae_rst(struct sh_dmae_device *shdev) { … } static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) { … } static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) { … } static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) { … } static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) { … } static void dmae_start(struct sh_dmae_chan *sh_chan) { … } static void dmae_init(struct sh_dmae_chan *sh_chan) { … } static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) { … } static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) { … } static void sh_dmae_start_xfer(struct shdma_chan *schan, struct shdma_desc *sdesc) { … } static bool sh_dmae_channel_busy(struct shdma_chan *schan) { … } static void sh_dmae_setup_xfer(struct shdma_chan *schan, int slave_id) { … } /* * Find a slave channel configuration from the controller list by either a slave * ID in the non-DT case, or by a MID/RID value in the DT case */ static const struct sh_dmae_slave_config *dmae_find_slave( struct sh_dmae_chan *sh_chan, int match) { … } static int sh_dmae_set_slave(struct shdma_chan *schan, int slave_id, dma_addr_t slave_addr, bool try) { … } static void dmae_halt(struct sh_dmae_chan *sh_chan) { … } static int sh_dmae_desc_setup(struct shdma_chan *schan, struct shdma_desc *sdesc, dma_addr_t src, dma_addr_t dst, size_t *len) { … } static void sh_dmae_halt(struct shdma_chan *schan) { … } static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq) { … } static size_t sh_dmae_get_partial(struct shdma_chan *schan, struct shdma_desc *sdesc) { … } /* Called from error IRQ or NMI */ static bool sh_dmae_reset(struct sh_dmae_device *shdev) { … } static irqreturn_t sh_dmae_err(int irq, void *data) { … } static bool sh_dmae_desc_completed(struct shdma_chan *schan, struct shdma_desc *sdesc) { … } static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev) { … } static int sh_dmae_nmi_handler(struct notifier_block *self, unsigned long cmd, void *data) { … } static struct notifier_block sh_dmae_nmi_notifier __read_mostly = …; static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, int irq, unsigned long flags) { … } static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) { … } #ifdef CONFIG_PM static int sh_dmae_runtime_suspend(struct device *dev) { … } static int sh_dmae_runtime_resume(struct device *dev) { … } #endif #ifdef CONFIG_PM_SLEEP static int sh_dmae_suspend(struct device *dev) { … } static int sh_dmae_resume(struct device *dev) { … } #endif static const struct dev_pm_ops sh_dmae_pm = …; static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan) { … } static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i) { … } static const struct shdma_ops sh_dmae_shdma_ops = …; static int sh_dmae_probe(struct platform_device *pdev) { … } static void sh_dmae_remove(struct platform_device *pdev) { … } static struct platform_driver sh_dmae_driver = …; static int __init sh_dmae_init(void) { … } module_init(…) …; static void __exit sh_dmae_exit(void) { … } module_exit(sh_dmae_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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