// SPDX-License-Identifier: GPL-2.0 /* * Lightning Mountain centralized DMA controller driver * * Copyright (c) 2016 - 2020 Intel Corporation. */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/err.h> #include <linux/export.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/iopoll.h> #include <linux/of_dma.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/reset.h> #include "../dmaengine.h" #include "../virt-dma.h" #define DRIVER_NAME … #define DMA_ID … #define DMA_ID_REV … #define DMA_ID_PNR … #define DMA_ID_CHNR … #define DMA_ID_DW_128B … #define DMA_ID_AW_36B … #define DMA_VER32 … #define DMA_VER31 … #define DMA_VER22 … #define DMA_CTRL … #define DMA_CTRL_RST … #define DMA_CTRL_DSRAM_PATH … #define DMA_CTRL_DBURST_WR … #define DMA_CTRL_VLD_DF_ACK … #define DMA_CTRL_CH_FL … #define DMA_CTRL_DS_FOD … #define DMA_CTRL_DRB … #define DMA_CTRL_ENBE … #define DMA_CTRL_DESC_TMOUT_CNT_V31 … #define DMA_CTRL_DESC_TMOUT_EN_V31 … #define DMA_CTRL_PKTARB … #define DMA_CPOLL … #define DMA_CPOLL_CNT … #define DMA_CPOLL_EN … #define DMA_CS … #define DMA_CS_MASK … #define DMA_CCTRL … #define DMA_CCTRL_ON … #define DMA_CCTRL_RST … #define DMA_CCTRL_CH_POLL_EN … #define DMA_CCTRL_CH_ABC … #define DMA_CDBA_MSB … #define DMA_CCTRL_DIR_TX … #define DMA_CCTRL_CLASS … #define DMA_CCTRL_CLASSH … #define DMA_CCTRL_WR_NP_EN … #define DMA_CCTRL_PDEN … #define DMA_MAX_CLASS … #define DMA_CDBA … #define DMA_CDLEN … #define DMA_CIS … #define DMA_CIE … #define DMA_CI_EOP … #define DMA_CI_DUR … #define DMA_CI_DESCPT … #define DMA_CI_CHOFF … #define DMA_CI_RDERR … #define DMA_CI_ALL … #define DMA_PS … #define DMA_PCTRL … #define DMA_PCTRL_RXBL16 … #define DMA_PCTRL_TXBL16 … #define DMA_PCTRL_RXBL … #define DMA_PCTRL_RXBL_8 … #define DMA_PCTRL_TXBL … #define DMA_PCTRL_TXBL_8 … #define DMA_PCTRL_PDEN … #define DMA_PCTRL_RXBL32 … #define DMA_PCTRL_RXENDI … #define DMA_PCTRL_TXENDI … #define DMA_PCTRL_TXBL32 … #define DMA_PCTRL_MEM_FLUSH … #define DMA_IRNEN1 … #define DMA_IRNCR1 … #define DMA_IRNEN … #define DMA_IRNCR … #define DMA_C_DP_TICK … #define DMA_C_DP_TICK_TIKNARB … #define DMA_C_DP_TICK_TIKARB … #define DMA_C_HDRM … /* * If header mode is set in DMA descriptor, * If bit 30 is disabled, HDR_LEN must be configured according to channel * requirement. * If bit 30 is enabled(checksum with header mode), HDR_LEN has no need to * be configured. It will enable check sum for switch * If header mode is not set in DMA descriptor, * This register setting doesn't matter */ #define DMA_C_HDRM_HDR_SUM … #define DMA_C_BOFF … #define DMA_C_BOFF_BOF_LEN … #define DMA_C_BOFF_EN … #define DMA_ORRC … #define DMA_ORRC_ORRCNT … #define DMA_ORRC_EN … #define DMA_C_ENDIAN … #define DMA_C_END_DATAENDI … #define DMA_C_END_DE_EN … #define DMA_C_END_DESENDI … #define DMA_C_END_DES_EN … /* DMA controller capability */ #define DMA_ADDR_36BIT … #define DMA_DATA_128BIT … #define DMA_CHAN_FLOW_CTL … #define DMA_DESC_FOD … #define DMA_DESC_IN_SRAM … #define DMA_EN_BYTE_EN … #define DMA_DBURST_WR … #define DMA_VALID_DESC_FETCH_ACK … #define DMA_DFT_DRB … #define DMA_ORRC_MAX_CNT … #define DMA_DFT_POLL_CNT … #define DMA_DFT_BURST_V22 … #define DMA_BURSTL_8DW … #define DMA_BURSTL_16DW … #define DMA_BURSTL_32DW … #define DMA_DFT_BURST … #define DMA_MAX_DESC_NUM … #define DMA_CHAN_BOFF_MAX … #define DMA_DFT_ENDIAN … #define DMA_DFT_DESC_TCNT … #define DMA_HDR_LEN_MAX … /* DMA flags */ #define DMA_TX_CH … #define DMA_RX_CH … #define DEVICE_ALLOC_DESC … #define CHAN_IN_USE … #define DMA_HW_DESC … /* Descriptor fields */ #define DESC_DATA_LEN … #define DESC_BYTE_OFF … #define DESC_EOP … #define DESC_SOP … #define DESC_C … #define DESC_OWN … #define DMA_CHAN_RST … #define DMA_MAX_SIZE … #define MAX_LOWER_CHANS … #define MASK_LOWER_CHANS … #define DMA_OWN … #define HIGH_4_BITS … #define DMA_DFT_DESC_NUM … #define DMA_PKT_DROP_DIS … enum ldma_chan_on_off { … }; enum { … }; struct ldma_dev; struct ldma_port; struct ldma_chan { … }; struct ldma_port { … }; /* Instance specific data */ struct ldma_inst_data { … }; struct ldma_dev { … }; struct dw2_desc { … } __packed __aligned(…); struct dw2_desc_sw { … }; static inline void ldma_update_bits(struct ldma_dev *d, u32 mask, u32 val, u32 ofs) { … } static inline struct ldma_chan *to_ldma_chan(struct dma_chan *chan) { … } static inline struct ldma_dev *to_ldma_dev(struct dma_device *dma_dev) { … } static inline struct dw2_desc_sw *to_lgm_dma_desc(struct virt_dma_desc *vdesc) { … } static inline bool ldma_chan_tx(struct ldma_chan *c) { … } static inline bool ldma_chan_is_hw_desc(struct ldma_chan *c) { … } static void ldma_dev_reset(struct ldma_dev *d) { … } static void ldma_dev_pkt_arb_cfg(struct ldma_dev *d, bool enable) { … } static void ldma_dev_sram_desc_cfg(struct ldma_dev *d, bool enable) { … } static void ldma_dev_chan_flow_ctl_cfg(struct ldma_dev *d, bool enable) { … } static void ldma_dev_global_polling_enable(struct ldma_dev *d) { … } static void ldma_dev_desc_fetch_on_demand_cfg(struct ldma_dev *d, bool enable) { … } static void ldma_dev_byte_enable_cfg(struct ldma_dev *d, bool enable) { … } static void ldma_dev_orrc_cfg(struct ldma_dev *d) { … } static void ldma_dev_df_tout_cfg(struct ldma_dev *d, bool enable, int tcnt) { … } static void ldma_dev_dburst_wr_cfg(struct ldma_dev *d, bool enable) { … } static void ldma_dev_vld_fetch_ack_cfg(struct ldma_dev *d, bool enable) { … } static void ldma_dev_drb_cfg(struct ldma_dev *d, int enable) { … } static int ldma_dev_cfg(struct ldma_dev *d) { … } static int ldma_chan_cctrl_cfg(struct ldma_chan *c, u32 val) { … } static void ldma_chan_irq_init(struct ldma_chan *c) { … } static void ldma_chan_set_class(struct ldma_chan *c, u32 val) { … } static int ldma_chan_on(struct ldma_chan *c) { … } static int ldma_chan_off(struct ldma_chan *c) { … } static void ldma_chan_desc_hw_cfg(struct ldma_chan *c, dma_addr_t desc_base, int desc_num) { … } static struct dma_async_tx_descriptor * ldma_chan_desc_cfg(struct dma_chan *chan, dma_addr_t desc_base, int desc_num) { … } static int ldma_chan_reset(struct ldma_chan *c) { … } static void ldma_chan_byte_offset_cfg(struct ldma_chan *c, u32 boff_len) { … } static void ldma_chan_data_endian_cfg(struct ldma_chan *c, bool enable, u32 endian_type) { … } static void ldma_chan_desc_endian_cfg(struct ldma_chan *c, bool enable, u32 endian_type) { … } static void ldma_chan_hdr_mode_cfg(struct ldma_chan *c, u32 hdr_len, bool csum) { … } static void ldma_chan_rxwr_np_cfg(struct ldma_chan *c, bool enable) { … } static void ldma_chan_abc_cfg(struct ldma_chan *c, bool enable) { … } static int ldma_port_cfg(struct ldma_port *p) { … } static int ldma_chan_cfg(struct ldma_chan *c) { … } static void ldma_dev_init(struct ldma_dev *d) { … } static int ldma_parse_dt(struct ldma_dev *d) { … } static void dma_free_desc_resource(struct virt_dma_desc *vdesc) { … } static struct dw2_desc_sw * dma_alloc_desc_resource(int num, struct ldma_chan *c) { … } static void ldma_chan_irq_en(struct ldma_chan *c) { … } static void ldma_issue_pending(struct dma_chan *chan) { … } static void ldma_synchronize(struct dma_chan *chan) { … } static int ldma_terminate_all(struct dma_chan *chan) { … } static int ldma_resume_chan(struct dma_chan *chan) { … } static int ldma_pause_chan(struct dma_chan *chan) { … } static enum dma_status ldma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { … } static void dma_chan_irq(int irq, void *data) { … } static irqreturn_t dma_interrupt(int irq, void *dev_id) { … } static void prep_slave_burst_len(struct ldma_chan *c) { … } static struct dma_async_tx_descriptor * ldma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen, enum dma_transfer_direction dir, unsigned long flags, void *context) { … } static int ldma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) { … } static int ldma_alloc_chan_resources(struct dma_chan *chan) { … } static void ldma_free_chan_resources(struct dma_chan *chan) { … } static void dma_work(struct work_struct *work) { … } static void update_burst_len_v22(struct ldma_chan *c, struct ldma_port *p, u32 burst) { … } static void update_burst_len_v3X(struct ldma_chan *c, struct ldma_port *p, u32 burst) { … } static int update_client_configs(struct of_dma *ofdma, struct of_phandle_args *spec) { … } static struct dma_chan *ldma_xlate(struct of_phandle_args *spec, struct of_dma *ofdma) { … } static void ldma_dma_init_v22(int i, struct ldma_dev *d) { … } static void ldma_dma_init_v3X(int i, struct ldma_dev *d) { … } static int ldma_init_v22(struct ldma_dev *d, struct platform_device *pdev) { … } static void ldma_clk_disable(void *data) { … } static const struct ldma_inst_data dma0 = …; static const struct ldma_inst_data dma2tx = …; static const struct ldma_inst_data dma1rx = …; static const struct ldma_inst_data dma1tx = …; static const struct ldma_inst_data dma0tx = …; static const struct ldma_inst_data dma3 = …; static const struct ldma_inst_data toe_dma30 = …; static const struct ldma_inst_data toe_dma31 = …; static const struct of_device_id intel_ldma_match[] = …; static int intel_ldma_probe(struct platform_device *pdev) { … } static struct platform_driver intel_ldma_driver = …; /* * Perform this driver as device_initcall to make sure initialization happens * before its DMA clients of some are platform specific and also to provide * registered DMA channels and DMA capabilities to clients before their * initialization. */ builtin_platform_driver(…) …;
Codebase Browser
linux