// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2018-2019 MediaTek Inc. /* * Driver for MediaTek Command-Queue DMA Controller * * Author: Shun-Chih Yu <[email protected]> * */ #include <linux/bitops.h> #include <linux/clk.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/err.h> #include <linux/iopoll.h> #include <linux/interrupt.h> #include <linux/list.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_dma.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/refcount.h> #include <linux/slab.h> #include "../virt-dma.h" #define MTK_CQDMA_USEC_POLL … #define MTK_CQDMA_TIMEOUT_POLL … #define MTK_CQDMA_DMA_BUSWIDTHS … #define MTK_CQDMA_ALIGN_SIZE … /* The default number of virtual channel */ #define MTK_CQDMA_NR_VCHANS … /* The default number of physical channel */ #define MTK_CQDMA_NR_PCHANS … /* Registers for underlying dma manipulation */ #define MTK_CQDMA_INT_FLAG … #define MTK_CQDMA_INT_EN … #define MTK_CQDMA_EN … #define MTK_CQDMA_RESET … #define MTK_CQDMA_FLUSH … #define MTK_CQDMA_SRC … #define MTK_CQDMA_DST … #define MTK_CQDMA_LEN1 … #define MTK_CQDMA_LEN2 … #define MTK_CQDMA_SRC2 … #define MTK_CQDMA_DST2 … /* Registers setting */ #define MTK_CQDMA_EN_BIT … #define MTK_CQDMA_INT_FLAG_BIT … #define MTK_CQDMA_INT_EN_BIT … #define MTK_CQDMA_FLUSH_BIT … #define MTK_CQDMA_WARM_RST_BIT … #define MTK_CQDMA_HARD_RST_BIT … #define MTK_CQDMA_MAX_LEN … #define MTK_CQDMA_ADDR_LIMIT … #define MTK_CQDMA_ADDR2_SHFIT … /** * struct mtk_cqdma_vdesc - The struct holding info describing virtual * descriptor (CVD) * @vd: An instance for struct virt_dma_desc * @len: The total data size device wants to move * @residue: The remaining data size device will move * @dest: The destination address device wants to move to * @src: The source address device wants to move from * @ch: The pointer to the corresponding dma channel * @node: The lise_head struct to build link-list for VDs * @parent: The pointer to the parent CVD */ struct mtk_cqdma_vdesc { … }; /** * struct mtk_cqdma_pchan - The struct holding info describing physical * channel (PC) * @queue: Queue for the PDs issued to this PC * @base: The mapped register I/O base of this PC * @irq: The IRQ that this PC are using * @refcnt: Track how many VCs are using this PC * @tasklet: Tasklet for this PC * @lock: Lock protect agaisting multiple VCs access PC */ struct mtk_cqdma_pchan { … }; /** * struct mtk_cqdma_vchan - The struct holding info describing virtual * channel (VC) * @vc: An instance for struct virt_dma_chan * @pc: The pointer to the underlying PC * @issue_completion: The wait for all issued descriptors completited * @issue_synchronize: Bool indicating channel synchronization starts */ struct mtk_cqdma_vchan { … }; /** * struct mtk_cqdma_device - The struct holding info describing CQDMA * device * @ddev: An instance for struct dma_device * @clk: The clock that device internal is using * @dma_requests: The number of VCs the device supports to * @dma_channels: The number of PCs the device supports to * @vc: The pointer to all available VCs * @pc: The pointer to all the underlying PCs */ struct mtk_cqdma_device { … }; static struct mtk_cqdma_device *to_cqdma_dev(struct dma_chan *chan) { … } static struct mtk_cqdma_vchan *to_cqdma_vchan(struct dma_chan *chan) { … } static struct mtk_cqdma_vdesc *to_cqdma_vdesc(struct virt_dma_desc *vd) { … } static struct device *cqdma2dev(struct mtk_cqdma_device *cqdma) { … } static u32 mtk_dma_read(struct mtk_cqdma_pchan *pc, u32 reg) { … } static void mtk_dma_write(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) { … } static void mtk_dma_rmw(struct mtk_cqdma_pchan *pc, u32 reg, u32 mask, u32 set) { … } static void mtk_dma_set(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) { … } static void mtk_dma_clr(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) { … } static void mtk_cqdma_vdesc_free(struct virt_dma_desc *vd) { … } static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc, bool atomic) { … } static int mtk_cqdma_hard_reset(struct mtk_cqdma_pchan *pc) { … } static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc, struct mtk_cqdma_vdesc *cvd) { … } static void mtk_cqdma_issue_vchan_pending(struct mtk_cqdma_vchan *cvc) { … } /* * return true if this VC is active, * meaning that there are VDs under processing by the PC */ static bool mtk_cqdma_is_vchan_active(struct mtk_cqdma_vchan *cvc) { … } /* * return the pointer of the CVD that is just consumed by the PC */ static struct mtk_cqdma_vdesc *mtk_cqdma_consume_work_queue(struct mtk_cqdma_pchan *pc) { … } static void mtk_cqdma_tasklet_cb(struct tasklet_struct *t) { … } static irqreturn_t mtk_cqdma_irq(int irq, void *devid) { … } static struct virt_dma_desc *mtk_cqdma_find_active_desc(struct dma_chan *c, dma_cookie_t cookie) { … } static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c, dma_cookie_t cookie, struct dma_tx_state *txstate) { … } static void mtk_cqdma_issue_pending(struct dma_chan *c) { … } static struct dma_async_tx_descriptor * mtk_cqdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) { … } static void mtk_cqdma_free_inactive_desc(struct dma_chan *c) { … } static void mtk_cqdma_free_active_desc(struct dma_chan *c) { … } static int mtk_cqdma_terminate_all(struct dma_chan *c) { … } static int mtk_cqdma_alloc_chan_resources(struct dma_chan *c) { … } static void mtk_cqdma_free_chan_resources(struct dma_chan *c) { … } static int mtk_cqdma_hw_init(struct mtk_cqdma_device *cqdma) { … } static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma) { … } static const struct of_device_id mtk_cqdma_match[] = …; MODULE_DEVICE_TABLE(of, mtk_cqdma_match); static int mtk_cqdma_probe(struct platform_device *pdev) { … } static void mtk_cqdma_remove(struct platform_device *pdev) { … } static struct platform_driver mtk_cqdma_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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