// SPDX-License-Identifier: GPL-2.0-only /* * TI EDMA DMA engine driver * * Copyright 2012 Texas Instruments */ #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/bitmap.h> #include <linux/err.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/list.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/of.h> #include <linux/of_dma.h> #include <linux/of_irq.h> #include <linux/of_address.h> #include <linux/pm_runtime.h> #include <linux/platform_data/edma.h> #include "../dmaengine.h" #include "../virt-dma.h" /* Offsets matching "struct edmacc_param" */ #define PARM_OPT … #define PARM_SRC … #define PARM_A_B_CNT … #define PARM_DST … #define PARM_SRC_DST_BIDX … #define PARM_LINK_BCNTRLD … #define PARM_SRC_DST_CIDX … #define PARM_CCNT … #define PARM_SIZE … /* Offsets for EDMA CC global channel registers and their shadows */ #define SH_ER … #define SH_ECR … #define SH_ESR … #define SH_CER … #define SH_EER … #define SH_EECR … #define SH_EESR … #define SH_SER … #define SH_SECR … #define SH_IER … #define SH_IECR … #define SH_IESR … #define SH_IPR … #define SH_ICR … #define SH_IEVAL … #define SH_QER … #define SH_QEER … #define SH_QEECR … #define SH_QEESR … #define SH_QSER … #define SH_QSECR … #define SH_SIZE … /* Offsets for EDMA CC global registers */ #define EDMA_REV … #define EDMA_CCCFG … #define EDMA_QCHMAP … #define EDMA_DMAQNUM … #define EDMA_QDMAQNUM … #define EDMA_QUETCMAP … #define EDMA_QUEPRI … #define EDMA_EMR … #define EDMA_EMCR … #define EDMA_QEMR … #define EDMA_QEMCR … #define EDMA_CCERR … #define EDMA_CCERRCLR … #define EDMA_EEVAL … #define EDMA_DRAE … #define EDMA_QRAE … #define EDMA_QUEEVTENTRY … #define EDMA_QSTAT … #define EDMA_QWMTHRA … #define EDMA_QWMTHRB … #define EDMA_CCSTAT … #define EDMA_M … #define EDMA_ECR … #define EDMA_ECRH … #define EDMA_SHADOW0 … #define EDMA_PARM … #define PARM_OFFSET(param_no) … #define EDMA_DCHMAP … /* CCCFG register */ #define GET_NUM_DMACH(x) … #define GET_NUM_QDMACH(x) … #define GET_NUM_PAENTRY(x) … #define GET_NUM_EVQUE(x) … #define GET_NUM_REGN(x) … #define CHMAP_EXIST … /* CCSTAT register */ #define EDMA_CCSTAT_ACTV … /* * Max of 20 segments per channel to conserve PaRAM slots * Also note that MAX_NR_SG should be at least the no.of periods * that are required for ASoC, otherwise DMA prep calls will * fail. Today davinci-pcm is the only user of this driver and * requires at least 17 slots, so we setup the default to 20. */ #define MAX_NR_SG … #define EDMA_MAX_SLOTS … #define EDMA_DESCRIPTORS … #define EDMA_CHANNEL_ANY … #define EDMA_SLOT_ANY … #define EDMA_CONT_PARAMS_ANY … #define EDMA_CONT_PARAMS_FIXED_EXACT … #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT … /* * 64bit array registers are split into two 32bit registers: * reg0: channel/event 0-31 * reg1: channel/event 32-63 * * bit 5 in the channel number tells the array index (0/1) * bit 0-4 (0x1f) is the bit offset within the register */ #define EDMA_REG_ARRAY_INDEX(channel) … #define EDMA_CHANNEL_BIT(channel) … /* PaRAM slots are laid out like this */ struct edmacc_param { … } __packed; /* fields in edmacc_param.opt */ #define SAM … #define DAM … #define SYNCDIM … #define STATIC … #define EDMA_FWID … #define TCCMODE … #define EDMA_TCC(t) … #define TCINTEN … #define ITCINTEN … #define TCCHEN … #define ITCCHEN … struct edma_pset { … }; struct edma_desc { … }; struct edma_cc; struct edma_tc { … }; struct edma_chan { … }; struct edma_cc { … }; /* dummy param set used to (re)initialize parameter RAM slots */ static const struct edmacc_param dummy_paramset = …; #define EDMA_BINDING_LEGACY … #define EDMA_BINDING_TPCC … static const u32 edma_binding_type[] = …; static const struct of_device_id edma_of_ids[] = …; MODULE_DEVICE_TABLE(of, edma_of_ids); static const struct of_device_id edma_tptc_of_ids[] = …; MODULE_DEVICE_TABLE(of, edma_tptc_of_ids); static inline unsigned int edma_read(struct edma_cc *ecc, int offset) { … } static inline void edma_write(struct edma_cc *ecc, int offset, int val) { … } static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, unsigned or) { … } static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) { … } static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, int i) { … } static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, unsigned val) { … } static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, unsigned and, unsigned or) { … } static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, unsigned or) { … } static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, int j, unsigned val) { … } static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, int offset, int i) { … } static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, unsigned val) { … } static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, int i, unsigned val) { … } static inline void edma_param_modify(struct edma_cc *ecc, int offset, int param_no, unsigned and, unsigned or) { … } static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, int priority) { … } static void edma_set_chmap(struct edma_chan *echan, int slot) { … } static void edma_setup_interrupt(struct edma_chan *echan, bool enable) { … } /* * paRAM slot management functions */ static void edma_write_slot(struct edma_cc *ecc, unsigned slot, const struct edmacc_param *param) { … } static int edma_read_slot(struct edma_cc *ecc, unsigned slot, struct edmacc_param *param) { … } /** * edma_alloc_slot - allocate DMA parameter RAM * @ecc: pointer to edma_cc struct * @slot: specific slot to allocate; negative for "any unused slot" * * This allocates a parameter RAM slot, initializing it to hold a * dummy transfer. Slots allocated using this routine have not been * mapped to a hardware DMA channel, and will normally be used by * linking to them from a slot associated with a DMA channel. * * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific * slots may be allocated on behalf of DSP firmware. * * Returns the number of the slot, else negative errno. */ static int edma_alloc_slot(struct edma_cc *ecc, int slot) { … } static void edma_free_slot(struct edma_cc *ecc, unsigned slot) { … } /** * edma_link - link one parameter RAM slot to another * @ecc: pointer to edma_cc struct * @from: parameter RAM slot originating the link * @to: parameter RAM slot which is the link target * * The originating slot should not be part of any active DMA transfer. */ static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) { … } /** * edma_get_position - returns the current transfer point * @ecc: pointer to edma_cc struct * @slot: parameter RAM slot being examined * @dst: true selects the dest position, false the source * * Returns the position of the current active slot */ static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, bool dst) { … } /* * Channels with event associations will be triggered by their hardware * events, and channels without such associations will be triggered by * software. (At this writing there is no interface for using software * triggers except with channels that don't support hardware triggers.) */ static void edma_start(struct edma_chan *echan) { … } static void edma_stop(struct edma_chan *echan) { … } /* * Temporarily disable EDMA hardware events on the specified channel, * preventing them from triggering new transfers */ static void edma_pause(struct edma_chan *echan) { … } /* Re-enable EDMA hardware events on the specified channel. */ static void edma_resume(struct edma_chan *echan) { … } static void edma_trigger_channel(struct edma_chan *echan) { … } static void edma_clean_channel(struct edma_chan *echan) { … } /* Move channel to a specific event queue */ static void edma_assign_channel_eventq(struct edma_chan *echan, enum dma_event_q eventq_no) { … } static int edma_alloc_channel(struct edma_chan *echan, enum dma_event_q eventq_no) { … } static void edma_free_channel(struct edma_chan *echan) { … } static inline struct edma_chan *to_edma_chan(struct dma_chan *c) { … } static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx) { … } static void edma_desc_free(struct virt_dma_desc *vdesc) { … } /* Dispatch a queued descriptor to the controller (caller holds lock) */ static void edma_execute(struct edma_chan *echan) { … } static int edma_terminate_all(struct dma_chan *chan) { … } static void edma_synchronize(struct dma_chan *chan) { … } static int edma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) { … } static int edma_dma_pause(struct dma_chan *chan) { … } static int edma_dma_resume(struct dma_chan *chan) { … } /* * A PaRAM set configuration abstraction used by other modes * @chan: Channel who's PaRAM set we're configuring * @pset: PaRAM set to initialize and setup. * @src_addr: Source address of the DMA * @dst_addr: Destination address of the DMA * @burst: In units of dev_width, how much to send * @dev_width: How much is the dev_width * @dma_length: Total length of the DMA transfer * @direction: Direction of the transfer */ static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, unsigned int acnt, unsigned int dma_length, enum dma_transfer_direction direction) { … } static struct dma_async_tx_descriptor *edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, unsigned long tx_flags, void *context) { … } static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long tx_flags) { … } static struct dma_async_tx_descriptor * edma_prep_dma_interleaved(struct dma_chan *chan, struct dma_interleaved_template *xt, unsigned long tx_flags) { … } static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long tx_flags) { … } static void edma_completion_handler(struct edma_chan *echan) { … } /* eDMA interrupt handler */ static irqreturn_t dma_irq_handler(int irq, void *data) { … } static void edma_error_handler(struct edma_chan *echan) { … } static inline bool edma_error_pending(struct edma_cc *ecc) { … } /* eDMA error interrupt handler */ static irqreturn_t dma_ccerr_handler(int irq, void *data) { … } /* Alloc channel resources */ static int edma_alloc_chan_resources(struct dma_chan *chan) { … } /* Free channel resources */ static void edma_free_chan_resources(struct dma_chan *chan) { … } /* Send pending descriptor to hardware */ static void edma_issue_pending(struct dma_chan *chan) { … } /* * This limit exists to avoid a possible infinite loop when waiting for proof * that a particular transfer is completed. This limit can be hit if there * are large bursts to/from slow devices or the CPU is never able to catch * the DMA hardware idle. On an AM335x transferring 48 bytes from the UART * RX-FIFO, as many as 55 loops have been seen. */ #define EDMA_MAX_TR_WAIT_LOOPS … static u32 edma_residue(struct edma_desc *edesc) { … } /* Check request completion status */ static enum dma_status edma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { … } static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels) { … } #define EDMA_DMA_BUSWIDTHS … static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) { … } static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, struct edma_cc *ecc) { … } #if IS_ENABLED(CONFIG_OF) static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, size_t sz) { … } static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, bool legacy_mode) { … } static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { … } #else static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, bool legacy_mode) { return ERR_PTR(-EINVAL); } static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { return NULL; } #endif static bool edma_filter_fn(struct dma_chan *chan, void *param); static int edma_probe(struct platform_device *pdev) { … } static void edma_cleanupp_vchan(struct dma_device *dmadev) { … } static void edma_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int edma_pm_suspend(struct device *dev) { … } static int edma_pm_resume(struct device *dev) { … } #endif static const struct dev_pm_ops edma_pm_ops = …; static struct platform_driver edma_driver = …; static int edma_tptc_probe(struct platform_device *pdev) { … } static struct platform_driver edma_tptc_driver = …; static bool edma_filter_fn(struct dma_chan *chan, void *param) { … } static int edma_init(void) { … } subsys_initcall(edma_init); static void __exit edma_exit(void) { … } module_exit(edma_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux