/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved. * Copyright (C) 2022, Advanced Micro Devices, Inc. */ #ifndef __DMA_XDMA_REGS_H #define __DMA_XDMA_REGS_H /* The length of register space exposed to host */ #define XDMA_REG_SPACE_LEN … /* * maximum number of DMA channels for each direction: * Host to Card (H2C) or Card to Host (C2H) */ #define XDMA_MAX_CHANNELS … /* * macros to define the number of descriptor blocks can be used in one * DMA transfer request. * the DMA engine uses a linked list of descriptor blocks that specify the * source, destination, and length of the DMA transfers. */ #define XDMA_DESC_BLOCK_NUM … #define XDMA_DESC_BLOCK_MASK … /* descriptor definitions */ #define XDMA_DESC_ADJACENT … #define XDMA_DESC_ADJACENT_MASK … #define XDMA_DESC_ADJACENT_BITS … #define XDMA_DESC_MAGIC … #define XDMA_DESC_MAGIC_BITS … #define XDMA_DESC_FLAGS_BITS … #define XDMA_DESC_STOPPED … #define XDMA_DESC_COMPLETED … #define XDMA_DESC_BLEN_BITS … #define XDMA_DESC_BLEN_MAX … /* macros to construct the descriptor control word */ #define XDMA_DESC_CONTROL(adjacent, flag) … #define XDMA_DESC_CONTROL_LAST … #define XDMA_DESC_CONTROL_CYCLIC … /* * Descriptor for a single contiguous memory block transfer. * * Multiple descriptors are linked by means of the next pointer. An additional * extra adjacent number gives the amount of extra contiguous descriptors. * * The descriptors are in root complex memory, and the bytes in the 32-bit * words must be in little-endian byte ordering. */ struct xdma_hw_desc { … }; #define XDMA_DESC_SIZE … #define XDMA_DESC_BLOCK_SIZE … #define XDMA_DESC_BLOCK_ALIGN … #define XDMA_DESC_BLOCK_BOUNDARY … /* * Channel registers */ #define XDMA_CHAN_IDENTIFIER … #define XDMA_CHAN_CONTROL … #define XDMA_CHAN_CONTROL_W1S … #define XDMA_CHAN_CONTROL_W1C … #define XDMA_CHAN_STATUS … #define XDMA_CHAN_STATUS_RC … #define XDMA_CHAN_COMPLETED_DESC … #define XDMA_CHAN_ALIGNMENTS … #define XDMA_CHAN_INTR_ENABLE … #define XDMA_CHAN_INTR_ENABLE_W1S … #define XDMA_CHAN_INTR_ENABLE_W1C … #define XDMA_CHAN_STRIDE … #define XDMA_CHAN_H2C_OFFSET … #define XDMA_CHAN_C2H_OFFSET … #define XDMA_CHAN_H2C_TARGET … #define XDMA_CHAN_C2H_TARGET … /* macro to check if channel is available */ #define XDMA_CHAN_MAGIC … #define XDMA_CHAN_CHECK_TARGET(id, target) … /* bits of the channel control register */ #define CHAN_CTRL_RUN_STOP … #define CHAN_CTRL_IE_DESC_STOPPED … #define CHAN_CTRL_IE_DESC_COMPLETED … #define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH … #define CHAN_CTRL_IE_MAGIC_STOPPED … #define CHAN_CTRL_IE_IDLE_STOPPED … #define CHAN_CTRL_IE_READ_ERROR … #define CHAN_CTRL_IE_WRITE_ERROR … #define CHAN_CTRL_IE_DESC_ERROR … #define CHAN_CTRL_NON_INCR_ADDR … #define CHAN_CTRL_POLL_MODE_WB … #define CHAN_CTRL_START … /* bits of the channel status register */ #define XDMA_CHAN_STATUS_BUSY … #define XDMA_CHAN_STATUS_MASK … #define XDMA_CHAN_ERROR_MASK … /* bits of the channel interrupt enable mask */ #define CHAN_IM_DESC_ERROR … #define CHAN_IM_READ_ERROR … #define CHAN_IM_IDLE_STOPPED … #define CHAN_IM_MAGIC_STOPPED … #define CHAN_IM_DESC_COMPLETED … #define CHAN_IM_DESC_STOPPED … #define CHAN_IM_ALL … /* * Channel SGDMA registers */ #define XDMA_SGDMA_IDENTIFIER … #define XDMA_SGDMA_DESC_LO … #define XDMA_SGDMA_DESC_HI … #define XDMA_SGDMA_DESC_ADJ … #define XDMA_SGDMA_DESC_CREDIT … /* * interrupt registers */ #define XDMA_IRQ_IDENTIFIER … #define XDMA_IRQ_USER_INT_EN … #define XDMA_IRQ_USER_INT_EN_W1S … #define XDMA_IRQ_USER_INT_EN_W1C … #define XDMA_IRQ_CHAN_INT_EN … #define XDMA_IRQ_CHAN_INT_EN_W1S … #define XDMA_IRQ_CHAN_INT_EN_W1C … #define XDMA_IRQ_USER_INT_REQ … #define XDMA_IRQ_CHAN_INT_REQ … #define XDMA_IRQ_USER_INT_PEND … #define XDMA_IRQ_CHAN_INT_PEND … #define XDMA_IRQ_USER_VEC_NUM … #define XDMA_IRQ_CHAN_VEC_NUM … #define XDMA_IRQ_VEC_SHIFT … #endif /* __DMA_XDMA_REGS_H */
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