// SPDX-License-Identifier: GPL-2.0-or-later /* * DMA driver for Altera mSGDMA IP core * * Copyright (C) 2017 Stefan Roese <[email protected]> * * Based on drivers/dma/xilinx/zynqmp_dma.c, which is: * Copyright (C) 2016 Xilinx, Inc. All rights reserved. */ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/of_dma.h> #include "dmaengine.h" #define MSGDMA_MAX_TRANS_LEN … #define MSGDMA_DESC_NUM … /** * struct msgdma_extended_desc - implements an extended descriptor * @read_addr_lo: data buffer source address low bits * @write_addr_lo: data buffer destination address low bits * @len: the number of bytes to transfer per descriptor * @burst_seq_num: bit 31:24 write burst * bit 23:16 read burst * bit 15:00 sequence number * @stride: bit 31:16 write stride * bit 15:00 read stride * @read_addr_hi: data buffer source address high bits * @write_addr_hi: data buffer destination address high bits * @control: characteristics of the transfer */ struct msgdma_extended_desc { … }; /* mSGDMA descriptor control field bit definitions */ #define MSGDMA_DESC_CTL_SET_CH(x) … #define MSGDMA_DESC_CTL_GEN_SOP … #define MSGDMA_DESC_CTL_GEN_EOP … #define MSGDMA_DESC_CTL_PARK_READS … #define MSGDMA_DESC_CTL_PARK_WRITES … #define MSGDMA_DESC_CTL_END_ON_EOP … #define MSGDMA_DESC_CTL_END_ON_LEN … #define MSGDMA_DESC_CTL_TR_COMP_IRQ … #define MSGDMA_DESC_CTL_EARLY_IRQ … #define MSGDMA_DESC_CTL_TR_ERR_IRQ … #define MSGDMA_DESC_CTL_EARLY_DONE … /* * Writing "1" the "go" bit commits the entire descriptor into the * descriptor FIFO(s) */ #define MSGDMA_DESC_CTL_GO … /* Tx buffer control flags */ #define MSGDMA_DESC_CTL_TX_FIRST … #define MSGDMA_DESC_CTL_TX_MIDDLE … #define MSGDMA_DESC_CTL_TX_LAST … #define MSGDMA_DESC_CTL_TX_SINGLE … #define MSGDMA_DESC_CTL_RX_SINGLE … /* mSGDMA extended descriptor stride definitions */ #define MSGDMA_DESC_STRIDE_RD … #define MSGDMA_DESC_STRIDE_WR … #define MSGDMA_DESC_STRIDE_RW … /* mSGDMA dispatcher control and status register map */ #define MSGDMA_CSR_STATUS … #define MSGDMA_CSR_CONTROL … #define MSGDMA_CSR_RW_FILL_LEVEL … /* 15:00 - read fill level */ #define MSGDMA_CSR_RESP_FILL_LEVEL … #define MSGDMA_CSR_RW_SEQ_NUM … /* 15:00 - read seq number */ /* mSGDMA CSR status register bit definitions */ #define MSGDMA_CSR_STAT_BUSY … #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY … #define MSGDMA_CSR_STAT_DESC_BUF_FULL … #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY … #define MSGDMA_CSR_STAT_RESP_BUF_FULL … #define MSGDMA_CSR_STAT_STOPPED … #define MSGDMA_CSR_STAT_RESETTING … #define MSGDMA_CSR_STAT_STOPPED_ON_ERR … #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY … #define MSGDMA_CSR_STAT_IRQ … #define MSGDMA_CSR_STAT_MASK … #define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ … #define DESC_EMPTY … /* mSGDMA CSR control register bit definitions */ #define MSGDMA_CSR_CTL_STOP … #define MSGDMA_CSR_CTL_RESET … #define MSGDMA_CSR_CTL_STOP_ON_ERR … #define MSGDMA_CSR_CTL_STOP_ON_EARLY … #define MSGDMA_CSR_CTL_GLOBAL_INTR … #define MSGDMA_CSR_CTL_STOP_DESCS … /* mSGDMA CSR fill level bits */ #define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) … #define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) … #define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) … #define MSGDMA_CSR_SEQ_NUM_GET(v) … /* mSGDMA response register map */ #define MSGDMA_RESP_BYTES_TRANSFERRED … #define MSGDMA_RESP_STATUS … /* mSGDMA response register bit definitions */ #define MSGDMA_RESP_EARLY_TERM … #define MSGDMA_RESP_ERR_MASK … /** * struct msgdma_sw_desc - implements a sw descriptor * @async_tx: support for the async_tx api * @hw_desc: associated HW descriptor * @node: node to move from the free list to the tx list * @tx_list: transmit list node */ struct msgdma_sw_desc { … }; /* * struct msgdma_device - DMA device structure */ struct msgdma_device { … }; #define to_mdev(chan) … #define tx_to_desc(tx) … /** * msgdma_get_descriptor - Get the sw descriptor from the pool * @mdev: Pointer to the Altera mSGDMA device structure * * Return: The sw descriptor */ static struct msgdma_sw_desc *msgdma_get_descriptor(struct msgdma_device *mdev) { … } /** * msgdma_free_descriptor - Issue pending transactions * @mdev: Pointer to the Altera mSGDMA device structure * @desc: Transaction descriptor pointer */ static void msgdma_free_descriptor(struct msgdma_device *mdev, struct msgdma_sw_desc *desc) { … } /** * msgdma_free_desc_list - Free descriptors list * @mdev: Pointer to the Altera mSGDMA device structure * @list: List to parse and delete the descriptor */ static void msgdma_free_desc_list(struct msgdma_device *mdev, struct list_head *list) { … } /** * msgdma_desc_config - Configure the descriptor * @desc: Hw descriptor pointer * @dst: Destination buffer address * @src: Source buffer address * @len: Transfer length * @stride: Read/write stride value to set */ static void msgdma_desc_config(struct msgdma_extended_desc *desc, dma_addr_t dst, dma_addr_t src, size_t len, u32 stride) { … } /** * msgdma_desc_config_eod - Mark the descriptor as end descriptor * @desc: Hw descriptor pointer */ static void msgdma_desc_config_eod(struct msgdma_extended_desc *desc) { … } /** * msgdma_tx_submit - Submit DMA transaction * @tx: Async transaction descriptor pointer * * Return: cookie value */ static dma_cookie_t msgdma_tx_submit(struct dma_async_tx_descriptor *tx) { … } /** * msgdma_prep_memcpy - prepare descriptors for memcpy transaction * @dchan: DMA channel * @dma_dst: Destination buffer address * @dma_src: Source buffer address * @len: Transfer length * @flags: transfer ack flags * * Return: Async transaction descriptor on success and NULL on failure */ static struct dma_async_tx_descriptor * msgdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, size_t len, ulong flags) { … } /** * msgdma_prep_slave_sg - prepare descriptors for a slave sg transaction * * @dchan: DMA channel * @sgl: Destination scatter list * @sg_len: Number of entries in destination scatter list * @dir: DMA transfer direction * @flags: transfer ack flags * @context: transfer context (unused) */ static struct dma_async_tx_descriptor * msgdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction dir, unsigned long flags, void *context) { … } static int msgdma_dma_config(struct dma_chan *dchan, struct dma_slave_config *config) { … } static void msgdma_reset(struct msgdma_device *mdev) { u32 val; int ret; /* Reset mSGDMA */ iowrite32(MSGDMA_CSR_STAT_MASK, mdev->csr + MSGDMA_CSR_STATUS); iowrite32(MSGDMA_CSR_CTL_RESET, mdev->csr + MSGDMA_CSR_CONTROL); ret = readl_poll_timeout(mdev->csr + MSGDMA_CSR_STATUS, val, (val & MSGDMA_CSR_STAT_RESETTING) == 0, 1, 10000); if (ret) dev_err(mdev->dev, "DMA channel did not reset\n"); /* Clear all status bits */ iowrite32(MSGDMA_CSR_STAT_MASK, mdev->csr + MSGDMA_CSR_STATUS); /* Enable the DMA controller including interrupts */ iowrite32(MSGDMA_CSR_CTL_STOP_ON_ERR | MSGDMA_CSR_CTL_STOP_ON_EARLY | MSGDMA_CSR_CTL_GLOBAL_INTR, mdev->csr + MSGDMA_CSR_CONTROL); mdev->idle = true; }; static void msgdma_copy_one(struct msgdma_device *mdev, struct msgdma_sw_desc *desc) { … } /** * msgdma_copy_desc_to_fifo - copy descriptor(s) into controller FIFO * @mdev: Pointer to the Altera mSGDMA device structure * @desc: Transaction descriptor pointer */ static void msgdma_copy_desc_to_fifo(struct msgdma_device *mdev, struct msgdma_sw_desc *desc) { … } /** * msgdma_start_transfer - Initiate the new transfer * @mdev: Pointer to the Altera mSGDMA device structure */ static void msgdma_start_transfer(struct msgdma_device *mdev) { … } /** * msgdma_issue_pending - Issue pending transactions * @chan: DMA channel pointer */ static void msgdma_issue_pending(struct dma_chan *chan) { … } /** * msgdma_chan_desc_cleanup - Cleanup the completed descriptors * @mdev: Pointer to the Altera mSGDMA device structure */ static void msgdma_chan_desc_cleanup(struct msgdma_device *mdev) { … } /** * msgdma_complete_descriptor - Mark the active descriptor as complete * @mdev: Pointer to the Altera mSGDMA device structure */ static void msgdma_complete_descriptor(struct msgdma_device *mdev) { … } /** * msgdma_free_descriptors - Free channel descriptors * @mdev: Pointer to the Altera mSGDMA device structure */ static void msgdma_free_descriptors(struct msgdma_device *mdev) { … } /** * msgdma_free_chan_resources - Free channel resources * @dchan: DMA channel pointer */ static void msgdma_free_chan_resources(struct dma_chan *dchan) { … } /** * msgdma_alloc_chan_resources - Allocate channel resources * @dchan: DMA channel * * Return: Number of descriptors on success and failure value on error */ static int msgdma_alloc_chan_resources(struct dma_chan *dchan) { … } /** * msgdma_tasklet - Schedule completion tasklet * @t: Pointer to the Altera sSGDMA channel structure */ static void msgdma_tasklet(struct tasklet_struct *t) { … } /** * msgdma_irq_handler - Altera mSGDMA Interrupt handler * @irq: IRQ number * @data: Pointer to the Altera mSGDMA device structure * * Return: IRQ_HANDLED/IRQ_NONE */ static irqreturn_t msgdma_irq_handler(int irq, void *data) { … } /** * msgdma_dev_remove() - Device remove function * @mdev: Pointer to the Altera mSGDMA device structure */ static void msgdma_dev_remove(struct msgdma_device *mdev) { … } static int request_and_map(struct platform_device *pdev, const char *name, struct resource **res, void __iomem **ptr, bool optional) { … } /** * msgdma_probe - Driver probe function * @pdev: Pointer to the platform_device structure * * Return: '0' on success and failure value on error */ static int msgdma_probe(struct platform_device *pdev) { … } /** * msgdma_remove() - Driver remove function * @pdev: Pointer to the platform_device structure * * Return: Always '0' */ static void msgdma_remove(struct platform_device *pdev) { … } #ifdef CONFIG_OF static const struct of_device_id msgdma_match[] = …; MODULE_DEVICE_TABLE(of, msgdma_match); #endif static struct platform_driver msgdma_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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