/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013-2014 Freescale Semiconductor, Inc. * Copyright 2018 Angelo Dureghello <[email protected]> */ #ifndef _FSL_EDMA_COMMON_H_ #define _FSL_EDMA_COMMON_H_ #include <linux/dma-direction.h> #include <linux/platform_device.h> #include "virt-dma.h" #define EDMA_CR_EDBG … #define EDMA_CR_ERCA … #define EDMA_CR_ERGA … #define EDMA_CR_HOE … #define EDMA_CR_HALT … #define EDMA_CR_CLM … #define EDMA_CR_EMLM … #define EDMA_CR_ECX … #define EDMA_CR_CX … #define EDMA_SEEI_SEEI(x) … #define EDMA_CEEI_CEEI(x) … #define EDMA_CINT_CINT(x) … #define EDMA_CERR_CERR(x) … #define EDMA_TCD_ATTR_DSIZE(x) … #define EDMA_TCD_ATTR_DMOD(x) … #define EDMA_TCD_ATTR_SSIZE(x) … #define EDMA_TCD_ATTR_SMOD(x) … #define EDMA_TCD_ITER_MASK … #define EDMA_TCD_CITER_CITER(x) … #define EDMA_TCD_BITER_BITER(x) … #define EDMA_TCD_CSR_START … #define EDMA_TCD_CSR_INT_MAJOR … #define EDMA_TCD_CSR_INT_HALF … #define EDMA_TCD_CSR_D_REQ … #define EDMA_TCD_CSR_E_SG … #define EDMA_TCD_CSR_E_LINK … #define EDMA_TCD_CSR_ACTIVE … #define EDMA_TCD_CSR_DONE … #define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) … #define EDMA_V3_TCD_NBYTES_MLOFF(x) … #define EDMA_V3_TCD_NBYTES_DMLOE … #define EDMA_V3_TCD_NBYTES_SMLOE … #define EDMAMUX_CHCFG_DIS … #define EDMAMUX_CHCFG_ENBL … #define EDMAMUX_CHCFG_SOURCE(n) … #define DMAMUX_NR … #define EDMA_TCD … #define FSL_EDMA_BUSWIDTHS … #define EDMA_V3_CH_SBR_RD … #define EDMA_V3_CH_SBR_WR … #define EDMA_V3_CH_CSR_ERQ … #define EDMA_V3_CH_CSR_EARQ … #define EDMA_V3_CH_CSR_EEI … #define EDMA_V3_CH_CSR_DONE … #define EDMA_V3_CH_CSR_ACTIVE … enum fsl_edma_pm_state { … }; struct fsl_edma_hw_tcd { … }; struct fsl_edma_hw_tcd64 { … } __packed; struct fsl_edma3_ch_reg { … } __packed; /* * These are iomem pointers, for both v32 and v64. */ struct edma_regs { … }; struct fsl_edma_sw_tcd { … }; struct fsl_edma_chan { … }; struct fsl_edma_desc { … }; #define FSL_EDMA_DRV_HAS_DMACLK … #define FSL_EDMA_DRV_MUX_SWAP … #define FSL_EDMA_DRV_CONFIG32 … #define FSL_EDMA_DRV_WRAP_IO … #define FSL_EDMA_DRV_EDMA64 … #define FSL_EDMA_DRV_HAS_PD … #define FSL_EDMA_DRV_HAS_CHCLK … #define FSL_EDMA_DRV_HAS_CHMUX … #define FSL_EDMA_DRV_MEM_REMOTE … /* control and status register is in tcd address space, edma3 reg layout */ #define FSL_EDMA_DRV_SPLIT_REG … #define FSL_EDMA_DRV_BUS_8BYTE … #define FSL_EDMA_DRV_DEV_TO_DEV … #define FSL_EDMA_DRV_ALIGN_64BYTE … /* Need clean CHn_CSR DONE before enable TCD's ESG */ #define FSL_EDMA_DRV_CLEAR_DONE_E_SG … /* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */ #define FSL_EDMA_DRV_CLEAR_DONE_E_LINK … #define FSL_EDMA_DRV_TCD64 … #define FSL_EDMA_DRV_EDMA3 … #define FSL_EDMA_DRV_EDMA4 … struct fsl_edma_drvdata { … }; struct fsl_edma_engine { … }; static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan) { … } #define edma_read_tcdreg_c(chan, _tcd, __name) … #define edma_read_tcdreg(chan, __name) … #define edma_write_tcdreg_c(chan, _tcd, _val, __name) … #define edma_write_tcdreg(chan, val, __name) … #define edma_cp_tcd_to_reg(chan, __tcd, __name) … #define edma_readl_chreg(chan, __name) … #define edma_writel_chreg(chan, val, __name) … #define fsl_edma_get_tcd(_chan, _tcd, _field) … #define fsl_edma_le_to_cpu(x) … #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) … #define fsl_edma_set_tcd_to_le_c(_tcd, _val, _field) … #define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field) … /* Need after struct defination */ #include "fsl-edma-trace.h" /* * R/W functions for big- or little-endian registers: * The eDMA controller's endian is independent of the CPU core's endian. * For the big-endian IP module, the offset for 8-bit or 16-bit registers * should also be swapped opposite to that in little-endian IP. */ static inline u64 edma_readq(struct fsl_edma_engine *edma, void __iomem *addr) { … } static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) { … } static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr) { … } static inline void edma_writeb(struct fsl_edma_engine *edma, u8 val, void __iomem *addr) { … } static inline void edma_writew(struct fsl_edma_engine *edma, u16 val, void __iomem *addr) { … } static inline void edma_writel(struct fsl_edma_engine *edma, u32 val, void __iomem *addr) { … } static inline void edma_writeq(struct fsl_edma_engine *edma, u64 val, void __iomem *addr) { … } static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan) { … } static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd) { … } static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan) { … } void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan); void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan); void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, unsigned int slot, bool enable); void fsl_edma_free_desc(struct virt_dma_desc *vdesc); int fsl_edma_terminate_all(struct dma_chan *chan); int fsl_edma_pause(struct dma_chan *chan); int fsl_edma_resume(struct dma_chan *chan); int fsl_edma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg); enum dma_status fsl_edma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate); struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long flags); struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, unsigned long flags, void *context); struct dma_async_tx_descriptor *fsl_edma_prep_memcpy( struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src, size_t len, unsigned long flags); void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan); void fsl_edma_issue_pending(struct dma_chan *chan); int fsl_edma_alloc_chan_resources(struct dma_chan *chan); void fsl_edma_free_chan_resources(struct dma_chan *chan); void fsl_edma_cleanup_vchan(struct dma_device *dmadev); void fsl_edma_setup_regs(struct fsl_edma_engine *edma); #endif /* _FSL_EDMA_COMMON_H_ */
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