// SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2019-2022 HiSilicon Limited. */ #include <linux/bitfield.h> #include <linux/dmaengine.h> #include <linux/init.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/spinlock.h> #include "virt-dma.h" /* HiSilicon DMA register common field define */ #define HISI_DMA_Q_SQ_BASE_L … #define HISI_DMA_Q_SQ_BASE_H … #define HISI_DMA_Q_SQ_DEPTH … #define HISI_DMA_Q_SQ_TAIL_PTR … #define HISI_DMA_Q_CQ_BASE_L … #define HISI_DMA_Q_CQ_BASE_H … #define HISI_DMA_Q_CQ_DEPTH … #define HISI_DMA_Q_CQ_HEAD_PTR … #define HISI_DMA_Q_CTRL0 … #define HISI_DMA_Q_CTRL0_QUEUE_EN … #define HISI_DMA_Q_CTRL0_QUEUE_PAUSE … #define HISI_DMA_Q_CTRL1 … #define HISI_DMA_Q_CTRL1_QUEUE_RESET … #define HISI_DMA_Q_FSM_STS … #define HISI_DMA_Q_FSM_STS_MASK … #define HISI_DMA_Q_ERR_INT_NUM0 … #define HISI_DMA_Q_ERR_INT_NUM1 … #define HISI_DMA_Q_ERR_INT_NUM2 … /* HiSilicon IP08 DMA register and field define */ #define HISI_DMA_HIP08_MODE … #define HISI_DMA_HIP08_Q_BASE … #define HISI_DMA_HIP08_Q_CTRL0_ERR_ABORT_EN … #define HISI_DMA_HIP08_Q_INT_STS … #define HISI_DMA_HIP08_Q_INT_MSK … #define HISI_DMA_HIP08_Q_INT_STS_MASK … #define HISI_DMA_HIP08_Q_ERR_INT_NUM3 … #define HISI_DMA_HIP08_Q_ERR_INT_NUM4 … #define HISI_DMA_HIP08_Q_ERR_INT_NUM5 … #define HISI_DMA_HIP08_Q_ERR_INT_NUM6 … #define HISI_DMA_HIP08_Q_CTRL0_SQCQ_DRCT … /* HiSilicon IP09 DMA register and field define */ #define HISI_DMA_HIP09_DMA_FLR_DISABLE … #define HISI_DMA_HIP09_DMA_FLR_DISABLE_B … #define HISI_DMA_HIP09_Q_BASE … #define HISI_DMA_HIP09_Q_CTRL0_ERR_ABORT_EN … #define HISI_DMA_HIP09_Q_CTRL0_SQ_DRCT … #define HISI_DMA_HIP09_Q_CTRL0_CQ_DRCT … #define HISI_DMA_HIP09_Q_CTRL1_VA_ENABLE … #define HISI_DMA_HIP09_Q_INT_STS … #define HISI_DMA_HIP09_Q_INT_MSK … #define HISI_DMA_HIP09_Q_INT_STS_MASK … #define HISI_DMA_HIP09_Q_ERR_INT_STS … #define HISI_DMA_HIP09_Q_ERR_INT_MSK … #define HISI_DMA_HIP09_Q_ERR_INT_STS_MASK … #define HISI_DMA_HIP09_PORT_CFG_REG(port_id) … #define HISI_DMA_HIP09_PORT_CFG_LINK_DOWN_MASK_B … #define HISI_DMA_HIP09_MAX_PORT_NUM … #define HISI_DMA_HIP08_MSI_NUM … #define HISI_DMA_HIP08_CHAN_NUM … #define HISI_DMA_HIP09_MSI_NUM … #define HISI_DMA_HIP09_CHAN_NUM … #define HISI_DMA_REVISION_HIP08B … #define HISI_DMA_REVISION_HIP09A … #define HISI_DMA_Q_OFFSET … #define HISI_DMA_Q_DEPTH_VAL … #define PCI_BAR_2 … #define HISI_DMA_POLL_Q_STS_DELAY_US … #define HISI_DMA_POLL_Q_STS_TIME_OUT_US … #define HISI_DMA_MAX_DIR_NAME_LEN … /* * The HIP08B(HiSilicon IP08) and HIP09A(HiSilicon IP09) are DMA iEPs, they * have the same pci device id but different pci revision. * Unfortunately, they have different register layouts, so two layout * enumerations are defined. */ enum hisi_dma_reg_layout { … }; enum hisi_dma_mode { … }; enum hisi_dma_chan_status { … }; struct hisi_dma_sqe { … }; struct hisi_dma_cqe { … }; struct hisi_dma_desc { … }; struct hisi_dma_chan { … }; struct hisi_dma_dev { … }; #ifdef CONFIG_DEBUG_FS static const struct debugfs_reg32 hisi_dma_comm_chan_regs[] = …; static const struct debugfs_reg32 hisi_dma_hip08_chan_regs[] = …; static const struct debugfs_reg32 hisi_dma_hip09_chan_regs[] = …; static const struct debugfs_reg32 hisi_dma_hip08_comm_regs[] = …; static const struct debugfs_reg32 hisi_dma_hip09_comm_regs[] = …; #endif /* CONFIG_DEBUG_FS*/ static enum hisi_dma_reg_layout hisi_dma_get_reg_layout(struct pci_dev *pdev) { … } static u32 hisi_dma_get_chan_num(struct pci_dev *pdev) { … } static u32 hisi_dma_get_msi_num(struct pci_dev *pdev) { … } static u32 hisi_dma_get_queue_base(struct pci_dev *pdev) { … } static inline struct hisi_dma_chan *to_hisi_dma_chan(struct dma_chan *c) { … } static inline struct hisi_dma_desc *to_hisi_dma_desc(struct virt_dma_desc *vd) { … } static inline void hisi_dma_chan_write(void __iomem *base, u32 reg, u32 index, u32 val) { … } static inline void hisi_dma_update_bit(void __iomem *addr, u32 pos, bool val) { … } static void hisi_dma_pause_dma(struct hisi_dma_dev *hdma_dev, u32 index, bool pause) { … } static void hisi_dma_enable_dma(struct hisi_dma_dev *hdma_dev, u32 index, bool enable) { … } static void hisi_dma_mask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index) { … } static void hisi_dma_unmask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index) { … } static void hisi_dma_do_reset(struct hisi_dma_dev *hdma_dev, u32 index) { … } static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index) { … } static void hisi_dma_reset_or_disable_hw_chan(struct hisi_dma_chan *chan, bool disable) { … } static void hisi_dma_free_chan_resources(struct dma_chan *c) { … } static void hisi_dma_desc_free(struct virt_dma_desc *vd) { … } static struct dma_async_tx_descriptor * hisi_dma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dst, dma_addr_t src, size_t len, unsigned long flags) { … } static enum dma_status hisi_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, struct dma_tx_state *txstate) { … } static void hisi_dma_start_transfer(struct hisi_dma_chan *chan) { … } static void hisi_dma_issue_pending(struct dma_chan *c) { … } static int hisi_dma_terminate_all(struct dma_chan *c) { … } static void hisi_dma_synchronize(struct dma_chan *c) { … } static int hisi_dma_alloc_qps_mem(struct hisi_dma_dev *hdma_dev) { … } static void hisi_dma_init_hw_qp(struct hisi_dma_dev *hdma_dev, u32 index) { … } static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index) { … } static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index) { … } static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev) { … } static void hisi_dma_disable_qps(struct hisi_dma_dev *hdma_dev) { … } static irqreturn_t hisi_dma_irq(int irq, void *data) { … } static int hisi_dma_request_qps_irq(struct hisi_dma_dev *hdma_dev) { … } /* This function enables all hw channels in a device */ static int hisi_dma_enable_hw_channels(struct hisi_dma_dev *hdma_dev) { … } static void hisi_dma_disable_hw_channels(void *data) { … } static void hisi_dma_set_mode(struct hisi_dma_dev *hdma_dev, enum hisi_dma_mode mode) { … } static void hisi_dma_init_hw(struct hisi_dma_dev *hdma_dev) { … } static void hisi_dma_init_dma_dev(struct hisi_dma_dev *hdma_dev) { … } /* --- debugfs implementation --- */ #ifdef CONFIG_DEBUG_FS #include <linux/debugfs.h> static struct debugfs_reg32 *hisi_dma_get_ch_regs(struct hisi_dma_dev *hdma_dev, u32 *regs_sz) { … } static int hisi_dma_create_chan_dir(struct hisi_dma_dev *hdma_dev) { … } static void hisi_dma_create_debugfs(struct hisi_dma_dev *hdma_dev) { … } #else static void hisi_dma_create_debugfs(struct hisi_dma_dev *hdma_dev) { } #endif /* CONFIG_DEBUG_FS*/ /* --- debugfs implementation --- */ static int hisi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *id) { … } static const struct pci_device_id hisi_dma_pci_tbl[] = …; static struct pci_driver hisi_dma_pci_driver = …; module_pci_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_DEVICE_TABLE(pci, hisi_dma_pci_tbl);
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