/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2007, 2008, Marvell International Ltd. */ #ifndef MV_XOR_H #define MV_XOR_H #include <linux/types.h> #include <linux/io.h> #include <linux/dmaengine.h> #include <linux/interrupt.h> #define MV_XOR_POOL_SIZE … #define MV_XOR_SLOT_SIZE … #define MV_XOR_THRESHOLD … #define MV_XOR_MAX_CHANNELS … #define MV_XOR_MIN_BYTE_COUNT … #define MV_XOR_MAX_BYTE_COUNT … /* Values for the XOR_CONFIG register */ #define XOR_OPERATION_MODE_XOR … #define XOR_OPERATION_MODE_MEMCPY … #define XOR_OPERATION_MODE_IN_DESC … #define XOR_DESCRIPTOR_SWAP … #define XOR_DESC_SUCCESS … #define XOR_DESC_OPERATION_XOR … #define XOR_DESC_OPERATION_CRC32C … #define XOR_DESC_OPERATION_MEMCPY … #define XOR_DESC_DMA_OWNED … #define XOR_DESC_EOD_INT_EN … #define XOR_CURR_DESC(chan) … #define XOR_NEXT_DESC(chan) … #define XOR_BYTE_COUNT(chan) … #define XOR_DEST_POINTER(chan) … #define XOR_BLOCK_SIZE(chan) … #define XOR_INIT_VALUE_LOW(chan) … #define XOR_INIT_VALUE_HIGH(chan) … #define XOR_CONFIG(chan) … #define XOR_ACTIVATION(chan) … #define XOR_INTR_CAUSE(chan) … #define XOR_INTR_MASK(chan) … #define XOR_ERROR_CAUSE(chan) … #define XOR_ERROR_ADDR(chan) … #define XOR_INT_END_OF_DESC … #define XOR_INT_END_OF_CHAIN … #define XOR_INT_STOPPED … #define XOR_INT_PAUSED … #define XOR_INT_ERR_DECODE … #define XOR_INT_ERR_RDPROT … #define XOR_INT_ERR_WRPROT … #define XOR_INT_ERR_OWN … #define XOR_INT_ERR_PAR … #define XOR_INT_ERR_MBUS … #define XOR_INTR_ERRORS … #define XOR_INTR_MASK_VALUE … #define WINDOW_BASE(w) … #define WINDOW_SIZE(w) … #define WINDOW_REMAP_HIGH(w) … #define WINDOW_BAR_ENABLE(chan) … #define WINDOW_OVERRIDE_CTRL(chan) … #define WINDOW_COUNT … struct mv_xor_device { … }; /** * struct mv_xor_chan - internal representation of a XOR channel * @pending: allows batching of hardware operations * @lock: serializes enqueue/dequeue operations to the descriptors pool * @mmr_base: memory mapped register base * @idx: the index of the xor channel * @chain: device chain view of the descriptors * @free_slots: free slots usable by the channel * @allocated_slots: slots allocated by the driver * @completed_slots: slots completed by HW but still need to be acked * @device: parent device * @common: common dmaengine channel object members * @slots_allocated: records the actual size of the descriptor slot pool * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs * @op_in_desc: new mode of driver, each op is written to descriptor. */ struct mv_xor_chan { … }; /** * struct mv_xor_desc_slot - software descriptor * @node: node on the mv_xor_chan lists * @hw_desc: virtual address of the hardware descriptor chain * @phys: hardware address of the hardware descriptor chain * @slot_used: slot in use or not * @idx: pool index * @tx_list: list of slots that make up a multi-descriptor transaction * @async_tx: support for the async_tx api */ struct mv_xor_desc_slot { … }; /* * This structure describes XOR descriptor size 64bytes. The * mv_phy_src_idx() macro must be used when indexing the values of the * phy_src_addr[] array. This is due to the fact that the 'descriptor * swap' feature, used on big endian systems, swaps descriptors data * within blocks of 8 bytes. So two consecutive values of the * phy_src_addr[] array are actually swapped in big-endian, which * explains the different mv_phy_src_idx() implementation. */ #if defined(__LITTLE_ENDIAN) struct mv_xor_desc { … }; #define mv_phy_src_idx(src_idx) … #else struct mv_xor_desc { u32 crc32_result; /* result of CRC-32 calculation */ u32 status; /* descriptor execution status */ u32 phy_next_desc; /* next descriptor address pointer */ u32 desc_command; /* type of operation to be carried out */ u32 phy_dest_addr; /* destination block address */ u32 byte_count; /* size of src/dst blocks in bytes */ u32 phy_src_addr[8]; /* source block addresses */ u32 reserved1; u32 reserved0; }; #define mv_phy_src_idx … #endif #define to_mv_sw_desc(addr_hw_desc) … #define mv_hw_desc_slot_idx(hw_desc, idx) … #endif
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