/* SPDX-License-Identifier: GPL-2.0-only */ /* * Driver for the Intel integrated DMA 64-bit * * Copyright (C) 2015 Intel Corporation */ #ifndef __DMA_IDMA64_H__ #define __DMA_IDMA64_H__ #include <linux/device.h> #include <linux/io.h> #include <linux/spinlock.h> #include <linux/types.h> #include <linux/io-64-nonatomic-lo-hi.h> #include "virt-dma.h" /* Channel registers */ #define IDMA64_CH_SAR … #define IDMA64_CH_DAR … #define IDMA64_CH_LLP … #define IDMA64_CH_CTL_LO … #define IDMA64_CH_CTL_HI … #define IDMA64_CH_SSTAT … #define IDMA64_CH_DSTAT … #define IDMA64_CH_SSTATAR … #define IDMA64_CH_DSTATAR … #define IDMA64_CH_CFG_LO … #define IDMA64_CH_CFG_HI … #define IDMA64_CH_SGR … #define IDMA64_CH_DSR … #define IDMA64_CH_LENGTH … /* Bitfields in CTL_LO */ #define IDMA64C_CTLL_INT_EN … #define IDMA64C_CTLL_DST_WIDTH(x) … #define IDMA64C_CTLL_SRC_WIDTH(x) … #define IDMA64C_CTLL_DST_INC … #define IDMA64C_CTLL_DST_FIX … #define IDMA64C_CTLL_SRC_INC … #define IDMA64C_CTLL_SRC_FIX … #define IDMA64C_CTLL_DST_MSIZE(x) … #define IDMA64C_CTLL_SRC_MSIZE(x) … #define IDMA64C_CTLL_FC_M2P … #define IDMA64C_CTLL_FC_P2M … #define IDMA64C_CTLL_LLP_D_EN … #define IDMA64C_CTLL_LLP_S_EN … /* Bitfields in CTL_HI */ #define IDMA64C_CTLH_BLOCK_TS_MASK … #define IDMA64C_CTLH_BLOCK_TS(x) … #define IDMA64C_CTLH_DONE … /* Bitfields in CFG_LO */ #define IDMA64C_CFGL_DST_BURST_ALIGN … #define IDMA64C_CFGL_SRC_BURST_ALIGN … #define IDMA64C_CFGL_CH_SUSP … #define IDMA64C_CFGL_FIFO_EMPTY … #define IDMA64C_CFGL_CH_DRAIN … #define IDMA64C_CFGL_DST_OPT_BL … #define IDMA64C_CFGL_SRC_OPT_BL … /* Bitfields in CFG_HI */ #define IDMA64C_CFGH_SRC_PER(x) … #define IDMA64C_CFGH_DST_PER(x) … #define IDMA64C_CFGH_RD_ISSUE_THD(x) … #define IDMA64C_CFGH_WR_ISSUE_THD(x) … /* Interrupt registers */ #define IDMA64_INT_XFER … #define IDMA64_INT_BLOCK … #define IDMA64_INT_SRC_TRAN … #define IDMA64_INT_DST_TRAN … #define IDMA64_INT_ERROR … #define IDMA64_RAW(x) … #define IDMA64_STATUS(x) … #define IDMA64_MASK(x) … #define IDMA64_CLEAR(x) … /* Common registers */ #define IDMA64_STATUS_INT … #define IDMA64_CFG … #define IDMA64_CH_EN … /* Bitfields in CFG */ #define IDMA64_CFG_DMA_EN … /* Hardware descriptor for Linked LIst transfers */ struct idma64_lli { … }; struct idma64_hw_desc { … }; struct idma64_desc { … }; static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc) { … } struct idma64_chan { … }; static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan) { … } #define channel_set_bit(idma64, reg, mask) … #define channel_clear_bit(idma64, reg, mask) … static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset) { … } static inline void idma64c_writel(struct idma64_chan *idma64c, int offset, u32 value) { … } #define channel_readl(idma64c, reg) … #define channel_writel(idma64c, reg, value) … static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset) { … } static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset, u64 value) { … } #define channel_readq(idma64c, reg) … #define channel_writeq(idma64c, reg, value) … struct idma64 { … }; static inline struct idma64 *to_idma64(struct dma_device *ddev) { … } static inline u32 idma64_readl(struct idma64 *idma64, int offset) { … } static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value) { … } #define dma_readl(idma64, reg) … #define dma_writel(idma64, reg, value) … /** * struct idma64_chip - representation of iDMA 64-bit controller hardware * @dev: struct device of the DMA controller * @sysdev: struct device of the physical device that does DMA * @irq: irq line * @regs: memory mapped I/O space * @idma64: struct idma64 that is filed by idma64_probe() */ struct idma64_chip { … }; #endif /* __DMA_IDMA64_H__ */
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