/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish <[email protected]> * Li Yang <[email protected]> * * Description: * QUICC Engine (QE) external definitions and structure. */ #ifndef _ASM_POWERPC_QE_H #define _ASM_POWERPC_QE_H #ifdef __KERNEL__ #include <linux/compiler.h> #include <linux/genalloc.h> #include <linux/spinlock.h> #include <linux/errno.h> #include <linux/err.h> #include <soc/fsl/cpm.h> #include <soc/fsl/qe/immap_qe.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/types.h> struct device; #define QE_NUM_OF_SNUM … #define QE_NUM_OF_BRGS … #define QE_NUM_OF_PORTS … /* Clocks and BRGs */ enum qe_clock { … }; static inline bool qe_clock_is_brg(enum qe_clock clk) { … } extern spinlock_t cmxgcr_lock; /* Export QE common operations */ #ifdef CONFIG_QUICC_ENGINE extern void qe_reset(void); #else static inline void qe_reset(void) {} #endif int cpm_muram_init(void); #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) s32 cpm_muram_alloc(unsigned long size, unsigned long align); s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size, unsigned long align); void cpm_muram_free(s32 offset); s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); s32 devm_cpm_muram_alloc_fixed(struct device *dev, unsigned long offset, unsigned long size); void __iomem *cpm_muram_addr(unsigned long offset); unsigned long cpm_muram_offset(const void __iomem *addr); dma_addr_t cpm_muram_dma(void __iomem *addr); void cpm_muram_free_addr(const void __iomem *addr); #else static inline s32 cpm_muram_alloc(unsigned long size, unsigned long align) { return -ENOSYS; } static inline s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size, unsigned long align) { return -ENOSYS; } static inline void cpm_muram_free(s32 offset) { } static inline s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size) { return -ENOSYS; } static inline s32 devm_cpm_muram_alloc_fixed(struct device *dev, unsigned long offset, unsigned long size) { return -ENOSYS; } static inline void __iomem *cpm_muram_addr(unsigned long offset) { return NULL; } static inline unsigned long cpm_muram_offset(const void __iomem *addr) { return -ENOSYS; } static inline dma_addr_t cpm_muram_dma(void __iomem *addr) { return 0; } static inline void cpm_muram_free_addr(const void __iomem *addr) { } #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */ /* QE PIO */ #define QE_PIO_PINS … struct qe_pio_regs { … }; #define QE_PIO_DIR_IN … #define QE_PIO_DIR_OUT … extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, int open_drain, int assignment, int has_irq); #ifdef CONFIG_QUICC_ENGINE extern int par_io_init(struct device_node *np); extern int par_io_of_config(struct device_node *np); extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, int assignment, int has_irq); extern int par_io_data_set(u8 port, u8 pin, u8 val); #else static inline int par_io_init(struct device_node *np) { return -ENOSYS; } static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, int assignment, int has_irq) { return -ENOSYS; } static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } #endif /* CONFIG_QUICC_ENGINE */ /* * Pin multiplexing functions. */ struct qe_pin; #ifdef CONFIG_QE_GPIO extern struct qe_pin *qe_pin_request(struct device *dev, int index); extern void qe_pin_free(struct qe_pin *qe_pin); extern void qe_pin_set_gpio(struct qe_pin *qe_pin); extern void qe_pin_set_dedicated(struct qe_pin *pin); #else static inline struct qe_pin *qe_pin_request(struct device *dev, int index) { … } static inline void qe_pin_free(struct qe_pin *qe_pin) { … } static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) { … } static inline void qe_pin_set_dedicated(struct qe_pin *pin) { … } #endif /* CONFIG_QE_GPIO */ #ifdef CONFIG_QUICC_ENGINE int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); #else static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) { return -ENOSYS; } #endif /* CONFIG_QUICC_ENGINE */ /* QE internal API */ enum qe_clock qe_clock_source(const char *source); unsigned int qe_get_brg_clk(void); int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); int qe_get_snum(void); void qe_put_snum(u8 snum); unsigned int qe_get_num_of_risc(void); unsigned int qe_get_num_of_snums(void); static inline int qe_alive_during_sleep(void) { … } /* we actually use cpm_muram implementation, define this for convenience */ #define qe_muram_init … #define qe_muram_alloc … #define devm_qe_muram_alloc … #define qe_muram_alloc_fixed … #define devm_qe_muram_alloc_fixed … #define qe_muram_free … #define qe_muram_addr … #define qe_muram_offset … #define qe_muram_dma … #define qe_muram_free_addr … #define qe_setbits_be32(_addr, _v) … #define qe_clrbits_be32(_addr, _v) … #define qe_setbits_be16(_addr, _v) … #define qe_clrbits_be16(_addr, _v) … #define qe_setbits_8(_addr, _v) … #define qe_clrbits_8(_addr, _v) … #define qe_clrsetbits_be32(addr, clear, set) … #define qe_clrsetbits_be16(addr, clear, set) … #define qe_clrsetbits_8(addr, clear, set) … /* Structure that defines QE firmware binary files. * * See Documentation/arch/powerpc/qe_firmware.rst for a description of these * fields. */ struct qe_firmware { … } __attribute__ ((packed)); struct qe_firmware_info { … }; #ifdef CONFIG_QUICC_ENGINE /* Upload a firmware to the QE */ int qe_upload_firmware(const struct qe_firmware *firmware); #else static inline int qe_upload_firmware(const struct qe_firmware *firmware) { return -ENOSYS; } #endif /* CONFIG_QUICC_ENGINE */ /* Obtain information on the uploaded firmware */ struct qe_firmware_info *qe_get_firmware_info(void); /* QE USB */ int qe_usb_clock_set(enum qe_clock clk, int rate); /* Buffer descriptors */ struct qe_bd { … } __attribute__ ((packed)); #define BD_STATUS_MASK … #define BD_LENGTH_MASK … /* Alignment */ #define QE_INTR_TABLE_ALIGN … #define QE_ALIGNMENT_OF_BD … #define QE_ALIGNMENT_OF_PRAM … /* RISC allocation */ #define QE_RISC_ALLOCATION_RISC1 … #define QE_RISC_ALLOCATION_RISC2 … #define QE_RISC_ALLOCATION_RISC3 … #define QE_RISC_ALLOCATION_RISC4 … #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 … #define QE_RISC_ALLOCATION_FOUR_RISCS … /* QE extended filtering Table Lookup Key Size */ enum qe_fltr_tbl_lookup_key_size { … }; /* QE FLTR extended filtering Largest External Table Lookup Key Size */ enum qe_fltr_largest_external_tbl_lookup_key_size { … }; /* structure representing QE parameter RAM */ struct qe_timer_tables { … } __attribute__ ((packed)); #define QE_FLTR_TAD_SIZE … /* QE extended filtering Termination Action Descriptor (TAD) */ struct qe_fltr_tad { … } __attribute__ ((packed)); /* Communication Direction */ enum comm_dir { … }; /* QE CMXUCR Registers. * There are two UCCs represented in each of the four CMXUCR registers. * These values are for the UCC in the LSBs */ #define QE_CMXUCR_MII_ENET_MNG … #define QE_CMXUCR_MII_ENET_MNG_SHIFT … #define QE_CMXUCR_GRANT … #define QE_CMXUCR_TSA … #define QE_CMXUCR_BKPT … #define QE_CMXUCR_TX_CLK_SRC_MASK … /* QE CMXGCR Registers. */ #define QE_CMXGCR_MII_ENET_MNG … #define QE_CMXGCR_MII_ENET_MNG_SHIFT … #define QE_CMXGCR_USBCS … #define QE_CMXGCR_USBCS_CLK3 … #define QE_CMXGCR_USBCS_CLK5 … #define QE_CMXGCR_USBCS_CLK7 … #define QE_CMXGCR_USBCS_CLK9 … #define QE_CMXGCR_USBCS_CLK13 … #define QE_CMXGCR_USBCS_CLK17 … #define QE_CMXGCR_USBCS_CLK19 … #define QE_CMXGCR_USBCS_CLK21 … #define QE_CMXGCR_USBCS_BRG9 … #define QE_CMXGCR_USBCS_BRG10 … /* QE CECR Commands. */ #define QE_CR_FLG … #define QE_RESET … #define QE_INIT_TX_RX … #define QE_INIT_RX … #define QE_INIT_TX … #define QE_ENTER_HUNT_MODE … #define QE_STOP_TX … #define QE_GRACEFUL_STOP_TX … #define QE_RESTART_TX … #define QE_CLOSE_RX_BD … #define QE_SWITCH_COMMAND … #define QE_SET_GROUP_ADDRESS … #define QE_START_IDMA … #define QE_MCC_STOP_RX … #define QE_ATM_TRANSMIT … #define QE_HPAC_CLEAR_ALL … #define QE_GRACEFUL_STOP_RX … #define QE_RESTART_RX … #define QE_HPAC_SET_PRIORITY … #define QE_HPAC_STOP_TX … #define QE_HPAC_STOP_RX … #define QE_HPAC_GRACEFUL_STOP_TX … #define QE_HPAC_GRACEFUL_STOP_RX … #define QE_HPAC_START_TX … #define QE_HPAC_START_RX … #define QE_USB_STOP_TX … #define QE_USB_RESTART_TX … #define QE_QMC_STOP_TX … #define QE_QMC_STOP_RX … #define QE_SS7_SU_FIL_RESET … #define QE_PUSHSCHED … /* jonathbr added from here down for 83xx */ #define QE_RESET_BCS … #define QE_MCC_INIT_TX_RX_16 … #define QE_MCC_STOP_TX … #define QE_MCC_INIT_TX_1 … #define QE_MCC_INIT_RX_1 … #define QE_MCC_RESET … #define QE_SET_TIMER … #define QE_RANDOM_NUMBER … #define QE_ATM_MULTI_THREAD_INIT … #define QE_ASSIGN_PAGE … #define QE_ADD_REMOVE_HASH_ENTRY … #define QE_START_FLOW_CONTROL … #define QE_STOP_FLOW_CONTROL … #define QE_ASSIGN_PAGE_TO_DEVICE … #define QE_ASSIGN_RISC … #define QE_CR_MCN_NORMAL_SHIFT … #define QE_CR_MCN_USB_SHIFT … #define QE_CR_MCN_RISC_ASSIGN_SHIFT … #define QE_CR_SNUM_SHIFT … /* QE CECR Sub Block - sub block of QE command. */ #define QE_CR_SUBBLOCK_INVALID … #define QE_CR_SUBBLOCK_USB … #define QE_CR_SUBBLOCK_UCCFAST1 … #define QE_CR_SUBBLOCK_UCCFAST2 … #define QE_CR_SUBBLOCK_UCCFAST3 … #define QE_CR_SUBBLOCK_UCCFAST4 … #define QE_CR_SUBBLOCK_UCCFAST5 … #define QE_CR_SUBBLOCK_UCCFAST6 … #define QE_CR_SUBBLOCK_UCCFAST7 … #define QE_CR_SUBBLOCK_UCCFAST8 … #define QE_CR_SUBBLOCK_UCCSLOW1 … #define QE_CR_SUBBLOCK_UCCSLOW2 … #define QE_CR_SUBBLOCK_UCCSLOW3 … #define QE_CR_SUBBLOCK_UCCSLOW4 … #define QE_CR_SUBBLOCK_UCCSLOW5 … #define QE_CR_SUBBLOCK_UCCSLOW6 … #define QE_CR_SUBBLOCK_UCCSLOW7 … #define QE_CR_SUBBLOCK_UCCSLOW8 … #define QE_CR_SUBBLOCK_MCC1 … #define QE_CR_SUBBLOCK_MCC2 … #define QE_CR_SUBBLOCK_MCC3 … #define QE_CR_SUBBLOCK_IDMA1 … #define QE_CR_SUBBLOCK_IDMA2 … #define QE_CR_SUBBLOCK_IDMA3 … #define QE_CR_SUBBLOCK_IDMA4 … #define QE_CR_SUBBLOCK_HPAC … #define QE_CR_SUBBLOCK_SPI1 … #define QE_CR_SUBBLOCK_SPI2 … #define QE_CR_SUBBLOCK_RAND … #define QE_CR_SUBBLOCK_TIMER … #define QE_CR_SUBBLOCK_GENERAL … /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ #define QE_CR_PROTOCOL_UNSPECIFIED … #define QE_CR_PROTOCOL_HDLC_TRANSPARENT … #define QE_CR_PROTOCOL_QMC … #define QE_CR_PROTOCOL_UART … #define QE_CR_PROTOCOL_ATM_POS … #define QE_CR_PROTOCOL_ETHERNET … #define QE_CR_PROTOCOL_L2_SWITCH … /* BRG configuration register */ #define QE_BRGC_ENABLE … #define QE_BRGC_DIVISOR_SHIFT … #define QE_BRGC_DIVISOR_MAX … #define QE_BRGC_DIV16 … /* QE Timers registers */ #define QE_GTCFR1_PCAS … #define QE_GTCFR1_STP2 … #define QE_GTCFR1_RST2 … #define QE_GTCFR1_GM2 … #define QE_GTCFR1_GM1 … #define QE_GTCFR1_STP1 … #define QE_GTCFR1_RST1 … /* SDMA registers */ #define QE_SDSR_BER1 … #define QE_SDSR_BER2 … #define QE_SDMR_GLB_1_MSK … #define QE_SDMR_ADR_SEL … #define QE_SDMR_BER1_MSK … #define QE_SDMR_BER2_MSK … #define QE_SDMR_EB1_MSK … #define QE_SDMR_ER1_MSK … #define QE_SDMR_ER2_MSK … #define QE_SDMR_CEN_MASK … #define QE_SDMR_SBER_1 … #define QE_SDMR_SBER_2 … #define QE_SDMR_EB1_PR_MASK … #define QE_SDMR_ER1_PR … #define QE_SDMR_CEN_SHIFT … #define QE_SDMR_EB1_PR_SHIFT … #define QE_SDTM_MSNUM_SHIFT … #define QE_SDEBCR_BA_MASK … /* Communication Processor */ #define QE_CP_CERCR_MEE … #define QE_CP_CERCR_IEE … #define QE_CP_CERCR_CIR … /* I-RAM */ #define QE_IRAM_IADD_AIE … #define QE_IRAM_IADD_BADDR … #define QE_IRAM_READY … /* UPC */ #define UPGCR_PROTOCOL … #define UPGCR_TMS … #define UPGCR_RMS … #define UPGCR_ADDR … #define UPGCR_DIAG … /* UCC GUEMR register */ #define UCC_GUEMR_MODE_MASK_RX … #define UCC_GUEMR_MODE_FAST_RX … #define UCC_GUEMR_MODE_SLOW_RX … #define UCC_GUEMR_MODE_MASK_TX … #define UCC_GUEMR_MODE_FAST_TX … #define UCC_GUEMR_MODE_SLOW_TX … #define UCC_GUEMR_MODE_MASK … #define UCC_GUEMR_SET_RESERVED3 … /* structure representing UCC SLOW parameter RAM */ struct ucc_slow_pram { … } __attribute__ ((packed)); /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ #define UCC_SLOW_GUMR_H_SAM_QMC … #define UCC_SLOW_GUMR_H_SAM_SATM … #define UCC_SLOW_GUMR_H_REVD … #define UCC_SLOW_GUMR_H_TRX … #define UCC_SLOW_GUMR_H_TTX … #define UCC_SLOW_GUMR_H_CDP … #define UCC_SLOW_GUMR_H_CTSP … #define UCC_SLOW_GUMR_H_CDS … #define UCC_SLOW_GUMR_H_CTSS … #define UCC_SLOW_GUMR_H_TFL … #define UCC_SLOW_GUMR_H_RFW … #define UCC_SLOW_GUMR_H_TXSY … #define UCC_SLOW_GUMR_H_4SYNC … #define UCC_SLOW_GUMR_H_8SYNC … #define UCC_SLOW_GUMR_H_16SYNC … #define UCC_SLOW_GUMR_H_RTSM … #define UCC_SLOW_GUMR_H_RSYN … #define UCC_SLOW_GUMR_L_TCI … #define UCC_SLOW_GUMR_L_RINV … #define UCC_SLOW_GUMR_L_TINV … #define UCC_SLOW_GUMR_L_TEND … #define UCC_SLOW_GUMR_L_TDCR_MASK … #define UCC_SLOW_GUMR_L_TDCR_32 … #define UCC_SLOW_GUMR_L_TDCR_16 … #define UCC_SLOW_GUMR_L_TDCR_8 … #define UCC_SLOW_GUMR_L_TDCR_1 … #define UCC_SLOW_GUMR_L_RDCR_MASK … #define UCC_SLOW_GUMR_L_RDCR_32 … #define UCC_SLOW_GUMR_L_RDCR_16 … #define UCC_SLOW_GUMR_L_RDCR_8 … #define UCC_SLOW_GUMR_L_RDCR_1 … #define UCC_SLOW_GUMR_L_RENC_NRZI … #define UCC_SLOW_GUMR_L_RENC_NRZ … #define UCC_SLOW_GUMR_L_TENC_NRZI … #define UCC_SLOW_GUMR_L_TENC_NRZ … #define UCC_SLOW_GUMR_L_DIAG_MASK … #define UCC_SLOW_GUMR_L_DIAG_LE … #define UCC_SLOW_GUMR_L_DIAG_ECHO … #define UCC_SLOW_GUMR_L_DIAG_LOOP … #define UCC_SLOW_GUMR_L_DIAG_NORM … #define UCC_SLOW_GUMR_L_ENR … #define UCC_SLOW_GUMR_L_ENT … #define UCC_SLOW_GUMR_L_MODE_MASK … #define UCC_SLOW_GUMR_L_MODE_BISYNC … #define UCC_SLOW_GUMR_L_MODE_AHDLC … #define UCC_SLOW_GUMR_L_MODE_UART … #define UCC_SLOW_GUMR_L_MODE_QMC … /* General UCC FAST Mode Register */ #define UCC_FAST_GUMR_LOOPBACK … #define UCC_FAST_GUMR_TCI … #define UCC_FAST_GUMR_TRX … #define UCC_FAST_GUMR_TTX … #define UCC_FAST_GUMR_CDP … #define UCC_FAST_GUMR_CTSP … #define UCC_FAST_GUMR_CDS … #define UCC_FAST_GUMR_CTSS … #define UCC_FAST_GUMR_TXSY … #define UCC_FAST_GUMR_RSYN … #define UCC_FAST_GUMR_SYNL_MASK … #define UCC_FAST_GUMR_SYNL_16 … #define UCC_FAST_GUMR_SYNL_8 … #define UCC_FAST_GUMR_SYNL_AUTO … #define UCC_FAST_GUMR_RTSM … #define UCC_FAST_GUMR_REVD … #define UCC_FAST_GUMR_ENR … #define UCC_FAST_GUMR_ENT … /* UART Slow UCC Event Register (UCCE) */ #define UCC_UART_UCCE_AB … #define UCC_UART_UCCE_IDLE … #define UCC_UART_UCCE_GRA … #define UCC_UART_UCCE_BRKE … #define UCC_UART_UCCE_BRKS … #define UCC_UART_UCCE_CCR … #define UCC_UART_UCCE_BSY … #define UCC_UART_UCCE_TX … #define UCC_UART_UCCE_RX … /* HDLC Slow UCC Event Register (UCCE) */ #define UCC_HDLC_UCCE_GLR … #define UCC_HDLC_UCCE_GLT … #define UCC_HDLC_UCCE_IDLE … #define UCC_HDLC_UCCE_BRKE … #define UCC_HDLC_UCCE_BRKS … #define UCC_HDLC_UCCE_TXE … #define UCC_HDLC_UCCE_RXF … #define UCC_HDLC_UCCE_BSY … #define UCC_HDLC_UCCE_TXB … #define UCC_HDLC_UCCE_RXB … /* BISYNC Slow UCC Event Register (UCCE) */ #define UCC_BISYNC_UCCE_GRA … #define UCC_BISYNC_UCCE_TXE … #define UCC_BISYNC_UCCE_RCH … #define UCC_BISYNC_UCCE_BSY … #define UCC_BISYNC_UCCE_TXB … #define UCC_BISYNC_UCCE_RXB … /* Gigabit Ethernet Fast UCC Event Register (UCCE) */ #define UCC_GETH_UCCE_MPD … #define UCC_GETH_UCCE_SCAR … #define UCC_GETH_UCCE_GRA … #define UCC_GETH_UCCE_CBPR … #define UCC_GETH_UCCE_BSY … #define UCC_GETH_UCCE_RXC … #define UCC_GETH_UCCE_TXC … #define UCC_GETH_UCCE_TXE … #define UCC_GETH_UCCE_TXB7 … #define UCC_GETH_UCCE_TXB6 … #define UCC_GETH_UCCE_TXB5 … #define UCC_GETH_UCCE_TXB4 … #define UCC_GETH_UCCE_TXB3 … #define UCC_GETH_UCCE_TXB2 … #define UCC_GETH_UCCE_TXB1 … #define UCC_GETH_UCCE_TXB0 … #define UCC_GETH_UCCE_RXB7 … #define UCC_GETH_UCCE_RXB6 … #define UCC_GETH_UCCE_RXB5 … #define UCC_GETH_UCCE_RXB4 … #define UCC_GETH_UCCE_RXB3 … #define UCC_GETH_UCCE_RXB2 … #define UCC_GETH_UCCE_RXB1 … #define UCC_GETH_UCCE_RXB0 … #define UCC_GETH_UCCE_RXF7 … #define UCC_GETH_UCCE_RXF6 … #define UCC_GETH_UCCE_RXF5 … #define UCC_GETH_UCCE_RXF4 … #define UCC_GETH_UCCE_RXF3 … #define UCC_GETH_UCCE_RXF2 … #define UCC_GETH_UCCE_RXF1 … #define UCC_GETH_UCCE_RXF0 … /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ #define UCC_UART_UPSMR_FLC … #define UCC_UART_UPSMR_SL … #define UCC_UART_UPSMR_CL_MASK … #define UCC_UART_UPSMR_CL_8 … #define UCC_UART_UPSMR_CL_7 … #define UCC_UART_UPSMR_CL_6 … #define UCC_UART_UPSMR_CL_5 … #define UCC_UART_UPSMR_UM_MASK … #define UCC_UART_UPSMR_UM_NORMAL … #define UCC_UART_UPSMR_UM_MAN_MULTI … #define UCC_UART_UPSMR_UM_AUTO_MULTI … #define UCC_UART_UPSMR_FRZ … #define UCC_UART_UPSMR_RZS … #define UCC_UART_UPSMR_SYN … #define UCC_UART_UPSMR_DRT … #define UCC_UART_UPSMR_PEN … #define UCC_UART_UPSMR_RPM_MASK … #define UCC_UART_UPSMR_RPM_ODD … #define UCC_UART_UPSMR_RPM_LOW … #define UCC_UART_UPSMR_RPM_EVEN … #define UCC_UART_UPSMR_RPM_HIGH … #define UCC_UART_UPSMR_TPM_MASK … #define UCC_UART_UPSMR_TPM_ODD … #define UCC_UART_UPSMR_TPM_LOW … #define UCC_UART_UPSMR_TPM_EVEN … #define UCC_UART_UPSMR_TPM_HIGH … /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */ #define UCC_GETH_UPSMR_FTFE … #define UCC_GETH_UPSMR_PTPE … #define UCC_GETH_UPSMR_ECM … #define UCC_GETH_UPSMR_HSE … #define UCC_GETH_UPSMR_PRO … #define UCC_GETH_UPSMR_CAP … #define UCC_GETH_UPSMR_RSH … #define UCC_GETH_UPSMR_RPM … #define UCC_GETH_UPSMR_R10M … #define UCC_GETH_UPSMR_RLPB … #define UCC_GETH_UPSMR_TBIM … #define UCC_GETH_UPSMR_RES1 … #define UCC_GETH_UPSMR_RMM … #define UCC_GETH_UPSMR_CAM … #define UCC_GETH_UPSMR_BRO … #define UCC_GETH_UPSMR_SMM … #define UCC_GETH_UPSMR_SGMM … /* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */ #define UCC_HDLC_UPSMR_RTE … #define UCC_HDLC_UPSMR_BUS … #define UCC_HDLC_UPSMR_CW8 … /* UCC Transmit On Demand Register (UTODR) */ #define UCC_SLOW_TOD … #define UCC_FAST_TOD … /* UCC Bus Mode Register masks */ /* Not to be confused with the Bundle Mode Register */ #define UCC_BMR_GBL … #define UCC_BMR_BO_BE … #define UCC_BMR_CETM … #define UCC_BMR_DTB … #define UCC_BMR_BDB … /* Function code masks */ #define FC_GBL … #define FC_DTB_LCL … #define UCC_FAST_FUNCTION_CODE_GBL … #define UCC_FAST_FUNCTION_CODE_DTB_LCL … #define UCC_FAST_FUNCTION_CODE_BDB_LCL … #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_QE_H */
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