/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. */ #ifndef _LINUX_QCOM_GENI_SE #define _LINUX_QCOM_GENI_SE #include <linux/interconnect.h> /** * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines * * @GENI_SE_INVALID: Invalid mode * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO * by programmed IO method * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred * with SE by DMAengine internal to SE * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine * configured by a firmware residing on a GSI engine. This DMA name is * interchangeably used as GSI or GPI which seem to imply the same DMAengine */ enum geni_se_xfer_mode { … }; /* Protocols supported by GENI Serial Engines */ enum geni_se_protocol_type { … }; struct geni_wrapper; struct clk; enum geni_icc_path_index { … }; struct geni_icc_path { … }; /** * struct geni_se - GENI Serial Engine * @base: Base Address of the Serial Engine's register block * @dev: Pointer to the Serial Engine device * @wrapper: Pointer to the parent QUP Wrapper core * @clk: Handle to the core serial engine clock * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE */ struct geni_se { … }; /* Common SE registers */ #define GENI_FORCE_DEFAULT_REG … #define GENI_OUTPUT_CTRL … #define SE_GENI_STATUS … #define GENI_SER_M_CLK_CFG … #define GENI_SER_S_CLK_CFG … #define GENI_IF_DISABLE_RO … #define GENI_FW_REVISION_RO … #define SE_GENI_CLK_SEL … #define SE_GENI_CFG_SEQ_START … #define SE_GENI_DMA_MODE_EN … #define SE_GENI_M_CMD0 … #define SE_GENI_M_CMD_CTRL_REG … #define SE_GENI_M_IRQ_STATUS … #define SE_GENI_M_IRQ_EN … #define SE_GENI_M_IRQ_CLEAR … #define SE_GENI_M_IRQ_EN_SET … #define SE_GENI_M_IRQ_EN_CLEAR … #define SE_GENI_S_CMD0 … #define SE_GENI_S_CMD_CTRL_REG … #define SE_GENI_S_IRQ_STATUS … #define SE_GENI_S_IRQ_EN … #define SE_GENI_S_IRQ_CLEAR … #define SE_GENI_S_IRQ_EN_SET … #define SE_GENI_S_IRQ_EN_CLEAR … #define SE_GENI_TX_FIFOn … #define SE_GENI_RX_FIFOn … #define SE_GENI_TX_FIFO_STATUS … #define SE_GENI_RX_FIFO_STATUS … #define SE_GENI_TX_WATERMARK_REG … #define SE_GENI_RX_WATERMARK_REG … #define SE_GENI_RX_RFR_WATERMARK_REG … #define SE_GENI_IOS … #define SE_GENI_M_GP_LENGTH … #define SE_GENI_S_GP_LENGTH … #define SE_DMA_TX_IRQ_STAT … #define SE_DMA_TX_IRQ_CLR … #define SE_DMA_TX_FSM_RST … #define SE_DMA_RX_IRQ_STAT … #define SE_DMA_RX_IRQ_CLR … #define SE_DMA_RX_LEN_IN … #define SE_DMA_RX_FSM_RST … #define SE_HW_PARAM_0 … #define SE_HW_PARAM_1 … /* GENI_FORCE_DEFAULT_REG fields */ #define FORCE_DEFAULT … /* GENI_OUTPUT_CTRL fields */ #define GENI_IO_MUX_0_EN … /* GENI_STATUS fields */ #define M_GENI_CMD_ACTIVE … #define S_GENI_CMD_ACTIVE … /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ #define SER_CLK_EN … #define CLK_DIV_MSK … #define CLK_DIV_SHFT … /* GENI_IF_DISABLE_RO fields */ #define FIFO_IF_DISABLE … /* GENI_FW_REVISION_RO fields */ #define FW_REV_PROTOCOL_MSK … #define FW_REV_PROTOCOL_SHFT … /* GENI_CLK_SEL fields */ #define CLK_SEL_MSK … /* SE_GENI_CFG_SEQ_START fields */ #define START_TRIGGER … /* SE_GENI_DMA_MODE_EN */ #define GENI_DMA_MODE_EN … /* GENI_M_CMD0 fields */ #define M_OPCODE_MSK … #define M_OPCODE_SHFT … #define M_PARAMS_MSK … /* GENI_M_CMD_CTRL_REG */ #define M_GENI_CMD_CANCEL … #define M_GENI_CMD_ABORT … #define M_GENI_DISABLE … /* GENI_S_CMD0 fields */ #define S_OPCODE_MSK … #define S_OPCODE_SHFT … #define S_PARAMS_MSK … /* GENI_S_CMD_CTRL_REG */ #define S_GENI_CMD_CANCEL … #define S_GENI_CMD_ABORT … #define S_GENI_DISABLE … /* GENI_M_IRQ_EN fields */ #define M_CMD_DONE_EN … #define M_CMD_OVERRUN_EN … #define M_ILLEGAL_CMD_EN … #define M_CMD_FAILURE_EN … #define M_CMD_CANCEL_EN … #define M_CMD_ABORT_EN … #define M_TIMESTAMP_EN … #define M_RX_IRQ_EN … #define M_GP_SYNC_IRQ_0_EN … #define M_GP_IRQ_0_EN … #define M_GP_IRQ_1_EN … #define M_GP_IRQ_2_EN … #define M_GP_IRQ_3_EN … #define M_GP_IRQ_4_EN … #define M_GP_IRQ_5_EN … #define M_TX_FIFO_NOT_EMPTY_EN … #define M_IO_DATA_DEASSERT_EN … #define M_IO_DATA_ASSERT_EN … #define M_RX_FIFO_RD_ERR_EN … #define M_RX_FIFO_WR_ERR_EN … #define M_RX_FIFO_WATERMARK_EN … #define M_RX_FIFO_LAST_EN … #define M_TX_FIFO_RD_ERR_EN … #define M_TX_FIFO_WR_ERR_EN … #define M_TX_FIFO_WATERMARK_EN … #define M_SEC_IRQ_EN … #define M_COMMON_GENI_M_IRQ_EN … /* GENI_S_IRQ_EN fields */ #define S_CMD_DONE_EN … #define S_CMD_OVERRUN_EN … #define S_ILLEGAL_CMD_EN … #define S_CMD_FAILURE_EN … #define S_CMD_CANCEL_EN … #define S_CMD_ABORT_EN … #define S_GP_SYNC_IRQ_0_EN … #define S_GP_IRQ_0_EN … #define S_GP_IRQ_1_EN … #define S_GP_IRQ_2_EN … #define S_GP_IRQ_3_EN … #define S_GP_IRQ_4_EN … #define S_GP_IRQ_5_EN … #define S_IO_DATA_DEASSERT_EN … #define S_IO_DATA_ASSERT_EN … #define S_RX_FIFO_RD_ERR_EN … #define S_RX_FIFO_WR_ERR_EN … #define S_RX_FIFO_WATERMARK_EN … #define S_RX_FIFO_LAST_EN … #define S_COMMON_GENI_S_IRQ_EN … /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ #define WATERMARK_MSK … /* GENI_TX_FIFO_STATUS fields */ #define TX_FIFO_WC … /* GENI_RX_FIFO_STATUS fields */ #define RX_LAST … #define RX_LAST_BYTE_VALID_MSK … #define RX_LAST_BYTE_VALID_SHFT … #define RX_FIFO_WC_MSK … /* SE_GENI_IOS fields */ #define IO2_DATA_IN … #define RX_DATA_IN … /* SE_GENI_M_GP_LENGTH and SE_GENI_S_GP_LENGTH fields */ #define GP_LENGTH … /* SE_DMA_TX_IRQ_STAT Register fields */ #define TX_DMA_DONE … #define TX_EOT … #define TX_SBE … #define TX_RESET_DONE … /* SE_DMA_RX_IRQ_STAT Register fields */ #define RX_DMA_DONE … #define RX_EOT … #define RX_SBE … #define RX_RESET_DONE … #define RX_FLUSH_DONE … #define RX_DMA_PARITY_ERR … #define RX_DMA_BREAK … #define RX_GENI_GP_IRQ … #define RX_GENI_GP_IRQ_EXT … #define RX_GENI_CANCEL_IRQ … /* SE_HW_PARAM_0 fields */ #define TX_FIFO_WIDTH_MSK … #define TX_FIFO_WIDTH_SHFT … /* * For QUP HW Version >= 3.10 Tx fifo depth support is increased * to 256bytes and corresponding bits are 16 to 23 */ #define TX_FIFO_DEPTH_MSK_256_BYTES … #define TX_FIFO_DEPTH_MSK … #define TX_FIFO_DEPTH_SHFT … /* SE_HW_PARAM_1 fields */ #define RX_FIFO_WIDTH_MSK … #define RX_FIFO_WIDTH_SHFT … /* * For QUP HW Version >= 3.10 Rx fifo depth support is increased * to 256bytes and corresponding bits are 16 to 23 */ #define RX_FIFO_DEPTH_MSK_256_BYTES … #define RX_FIFO_DEPTH_MSK … #define RX_FIFO_DEPTH_SHFT … #define HW_VER_MAJOR_MASK … #define HW_VER_MAJOR_SHFT … #define HW_VER_MINOR_MASK … #define HW_VER_MINOR_SHFT … #define HW_VER_STEP_MASK … #define GENI_SE_VERSION_MAJOR(ver) … #define GENI_SE_VERSION_MINOR(ver) … #define GENI_SE_VERSION_STEP(ver) … /* QUP SE VERSION value for major number 2 and minor number 5 */ #define QUP_SE_VERSION_2_5 … /* * Define bandwidth thresholds that cause the underlying Core 2X interconnect * clock to run at the named frequency. These baseline values are recommended * by the hardware team, and are not dynamically scaled with GENI bandwidth * beyond basic on/off. */ #define CORE_2X_19_2_MHZ … #define CORE_2X_50_MHZ … #define CORE_2X_100_MHZ … #define CORE_2X_150_MHZ … #define CORE_2X_200_MHZ … #define CORE_2X_236_MHZ … #define GENI_DEFAULT_BW … #if IS_ENABLED(CONFIG_QCOM_GENI_SE) u32 geni_se_get_qup_hw_version(struct geni_se *se); /** * geni_se_read_proto() - Read the protocol configured for a serial engine * @se: Pointer to the concerned serial engine. * * Return: Protocol value as configured in the serial engine. */ static inline u32 geni_se_read_proto(struct geni_se *se) { … } /** * geni_se_setup_m_cmd() - Setup the primary sequencer * @se: Pointer to the concerned serial engine. * @cmd: Command/Operation to setup in the primary sequencer. * @params: Parameter for the sequencer command. * * This function is used to configure the primary sequencer with the * command and its associated parameters. */ static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params) { … } /** * geni_se_setup_s_cmd() - Setup the secondary sequencer * @se: Pointer to the concerned serial engine. * @cmd: Command/Operation to setup in the secondary sequencer. * @params: Parameter for the sequencer command. * * This function is used to configure the secondary sequencer with the * command and its associated parameters. */ static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params) { … } /** * geni_se_cancel_m_cmd() - Cancel the command configured in the primary * sequencer * @se: Pointer to the concerned serial engine. * * This function is used to cancel the currently configured command in the * primary sequencer. */ static inline void geni_se_cancel_m_cmd(struct geni_se *se) { … } /** * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary * sequencer * @se: Pointer to the concerned serial engine. * * This function is used to cancel the currently configured command in the * secondary sequencer. */ static inline void geni_se_cancel_s_cmd(struct geni_se *se) { … } /** * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer * @se: Pointer to the concerned serial engine. * * This function is used to force abort the currently configured command in the * primary sequencer. */ static inline void geni_se_abort_m_cmd(struct geni_se *se) { … } /** * geni_se_abort_s_cmd() - Abort the command configured in the secondary * sequencer * @se: Pointer to the concerned serial engine. * * This function is used to force abort the currently configured command in the * secondary sequencer. */ static inline void geni_se_abort_s_cmd(struct geni_se *se) { … } /** * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine * based on QUP HW version * @se: Pointer to the concerned serial engine. * * This function is used to get the depth i.e. number of elements in the * TX fifo of the serial engine. * * Return: TX fifo depth in units of FIFO words. */ static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) { … } /** * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine * @se: Pointer to the concerned serial engine. * * This function is used to get the width i.e. word size per element in the * TX fifo of the serial engine. * * Return: TX fifo width in bits */ static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) { … } /** * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine * based on QUP HW version * @se: Pointer to the concerned serial engine. * * This function is used to get the depth i.e. number of elements in the * RX fifo of the serial engine. * * Return: RX fifo depth in units of FIFO words */ static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) { … } void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode); void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, bool msb_to_lsb, bool tx_cfg, bool rx_cfg); int geni_se_resources_off(struct geni_se *se); int geni_se_resources_on(struct geni_se *se); int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl); int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, unsigned int *index, unsigned long *res_freq, bool exact); void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, dma_addr_t *iova); void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len); int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, dma_addr_t *iova); void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); int geni_icc_get(struct geni_se *se, const char *icc_ddr); int geni_icc_set_bw(struct geni_se *se); void geni_icc_set_tag(struct geni_se *se, u32 tag); int geni_icc_enable(struct geni_se *se); int geni_icc_disable(struct geni_se *se); #endif #endif
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