// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2017 Impinj, Inc * Author: Andrey Smirnov <[email protected]> * * Based on the code of analogus driver: * * Copyright 2015-2017 Pengutronix, Lucas Stach <[email protected]> */ #include <linux/clk.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/reset.h> #include <linux/sizes.h> #include <dt-bindings/power/imx7-power.h> #include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/power/imx8mm-power.h> #include <dt-bindings/power/imx8mn-power.h> #include <dt-bindings/power/imx8mp-power.h> #define GPC_LPCR_A_CORE_BSC … #define GPC_PGC_CPU_MAPPING … #define IMX8MP_GPC_PGC_CPU_MAPPING … #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN … #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN … #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN … #define IMX7_PCIE_PHY_A_CORE_DOMAIN … #define IMX7_MIPI_PHY_A_CORE_DOMAIN … #define IMX8M_PCIE2_A53_DOMAIN … #define IMX8M_MIPI_CSI2_A53_DOMAIN … #define IMX8M_MIPI_CSI1_A53_DOMAIN … #define IMX8M_DISP_A53_DOMAIN … #define IMX8M_HDMI_A53_DOMAIN … #define IMX8M_VPU_A53_DOMAIN … #define IMX8M_GPU_A53_DOMAIN … #define IMX8M_DDR2_A53_DOMAIN … #define IMX8M_DDR1_A53_DOMAIN … #define IMX8M_OTG2_A53_DOMAIN … #define IMX8M_OTG1_A53_DOMAIN … #define IMX8M_PCIE1_A53_DOMAIN … #define IMX8M_MIPI_A53_DOMAIN … #define IMX8MM_VPUH1_A53_DOMAIN … #define IMX8MM_VPUG2_A53_DOMAIN … #define IMX8MM_VPUG1_A53_DOMAIN … #define IMX8MM_DISPMIX_A53_DOMAIN … #define IMX8MM_VPUMIX_A53_DOMAIN … #define IMX8MM_GPUMIX_A53_DOMAIN … #define IMX8MM_GPU_A53_DOMAIN … #define IMX8MM_DDR1_A53_DOMAIN … #define IMX8MM_OTG2_A53_DOMAIN … #define IMX8MM_OTG1_A53_DOMAIN … #define IMX8MM_PCIE_A53_DOMAIN … #define IMX8MM_MIPI_A53_DOMAIN … #define IMX8MN_DISPMIX_A53_DOMAIN … #define IMX8MN_GPUMIX_A53_DOMAIN … #define IMX8MN_DDR1_A53_DOMAIN … #define IMX8MN_OTG1_A53_DOMAIN … #define IMX8MN_MIPI_A53_DOMAIN … #define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN … #define IMX8MP_HSIOMIX_A53_DOMAIN … #define IMX8MP_MIPI_PHY2_A53_DOMAIN … #define IMX8MP_HDMI_PHY_A53_DOMAIN … #define IMX8MP_HDMIMIX_A53_DOMAIN … #define IMX8MP_VPU_VC8000E_A53_DOMAIN … #define IMX8MP_VPU_G2_A53_DOMAIN … #define IMX8MP_VPU_G1_A53_DOMAIN … #define IMX8MP_MEDIAMIX_A53_DOMAIN … #define IMX8MP_GPU3D_A53_DOMAIN … #define IMX8MP_VPUMIX_A53_DOMAIN … #define IMX8MP_GPUMIX_A53_DOMAIN … #define IMX8MP_GPU2D_A53_DOMAIN … #define IMX8MP_AUDIOMIX_A53_DOMAIN … #define IMX8MP_MLMIX_A53_DOMAIN … #define IMX8MP_USB2_PHY_A53_DOMAIN … #define IMX8MP_USB1_PHY_A53_DOMAIN … #define IMX8MP_PCIE_PHY_A53_DOMAIN … #define IMX8MP_MIPI_PHY1_A53_DOMAIN … #define IMX8MP_GPC_PU_PGC_SW_PUP_REQ … #define IMX8MP_GPC_PU_PGC_SW_PDN_REQ … #define GPC_PU_PGC_SW_PUP_REQ … #define GPC_PU_PGC_SW_PDN_REQ … #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ … #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ … #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ … #define IMX7_PCIE_PHY_SW_Pxx_REQ … #define IMX7_MIPI_PHY_SW_Pxx_REQ … #define IMX8M_PCIE2_SW_Pxx_REQ … #define IMX8M_MIPI_CSI2_SW_Pxx_REQ … #define IMX8M_MIPI_CSI1_SW_Pxx_REQ … #define IMX8M_DISP_SW_Pxx_REQ … #define IMX8M_HDMI_SW_Pxx_REQ … #define IMX8M_VPU_SW_Pxx_REQ … #define IMX8M_GPU_SW_Pxx_REQ … #define IMX8M_DDR2_SW_Pxx_REQ … #define IMX8M_DDR1_SW_Pxx_REQ … #define IMX8M_OTG2_SW_Pxx_REQ … #define IMX8M_OTG1_SW_Pxx_REQ … #define IMX8M_PCIE1_SW_Pxx_REQ … #define IMX8M_MIPI_SW_Pxx_REQ … #define IMX8MM_VPUH1_SW_Pxx_REQ … #define IMX8MM_VPUG2_SW_Pxx_REQ … #define IMX8MM_VPUG1_SW_Pxx_REQ … #define IMX8MM_DISPMIX_SW_Pxx_REQ … #define IMX8MM_VPUMIX_SW_Pxx_REQ … #define IMX8MM_GPUMIX_SW_Pxx_REQ … #define IMX8MM_GPU_SW_Pxx_REQ … #define IMX8MM_DDR1_SW_Pxx_REQ … #define IMX8MM_OTG2_SW_Pxx_REQ … #define IMX8MM_OTG1_SW_Pxx_REQ … #define IMX8MM_PCIE_SW_Pxx_REQ … #define IMX8MM_MIPI_SW_Pxx_REQ … #define IMX8MN_DISPMIX_SW_Pxx_REQ … #define IMX8MN_GPUMIX_SW_Pxx_REQ … #define IMX8MN_DDR1_SW_Pxx_REQ … #define IMX8MN_OTG1_SW_Pxx_REQ … #define IMX8MN_MIPI_SW_Pxx_REQ … #define IMX8MP_DDRMIX_Pxx_REQ … #define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ … #define IMX8MP_HSIOMIX_Pxx_REQ … #define IMX8MP_MIPI_PHY2_Pxx_REQ … #define IMX8MP_HDMI_PHY_Pxx_REQ … #define IMX8MP_HDMIMIX_Pxx_REQ … #define IMX8MP_VPU_VC8K_Pxx_REQ … #define IMX8MP_VPU_G2_Pxx_REQ … #define IMX8MP_VPU_G1_Pxx_REQ … #define IMX8MP_MEDIMIX_Pxx_REQ … #define IMX8MP_GPU_3D_Pxx_REQ … #define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ … #define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ … #define IMX8MP_GPU_2D_Pxx_REQ … #define IMX8MP_AUDIOMIX_Pxx_REQ … #define IMX8MP_MLMIX_Pxx_REQ … #define IMX8MP_USB2_PHY_Pxx_REQ … #define IMX8MP_USB1_PHY_Pxx_REQ … #define IMX8MP_PCIE_PHY_SW_Pxx_REQ … #define IMX8MP_MIPI_PHY1_SW_Pxx_REQ … #define GPC_M4_PU_PDN_FLG … #define IMX8MP_GPC_PU_PWRHSK … #define GPC_PU_PWRHSK … #define IMX8M_GPU_HSK_PWRDNACKN … #define IMX8M_VPU_HSK_PWRDNACKN … #define IMX8M_DISP_HSK_PWRDNACKN … #define IMX8M_GPU_HSK_PWRDNREQN … #define IMX8M_VPU_HSK_PWRDNREQN … #define IMX8M_DISP_HSK_PWRDNREQN … #define IMX8MM_GPUMIX_HSK_PWRDNACKN … #define IMX8MM_GPU_HSK_PWRDNACKN … #define IMX8MM_VPUMIX_HSK_PWRDNACKN … #define IMX8MM_DISPMIX_HSK_PWRDNACKN … #define IMX8MM_HSIO_HSK_PWRDNACKN … #define IMX8MM_GPUMIX_HSK_PWRDNREQN … #define IMX8MM_GPU_HSK_PWRDNREQN … #define IMX8MM_VPUMIX_HSK_PWRDNREQN … #define IMX8MM_DISPMIX_HSK_PWRDNREQN … #define IMX8MM_HSIO_HSK_PWRDNREQN … #define IMX8MN_GPUMIX_HSK_PWRDNACKN … #define IMX8MN_DISPMIX_HSK_PWRDNACKN … #define IMX8MN_HSIO_HSK_PWRDNACKN … #define IMX8MN_GPUMIX_HSK_PWRDNREQN … #define IMX8MN_DISPMIX_HSK_PWRDNREQN … #define IMX8MN_HSIO_HSK_PWRDNREQN … #define IMX8MP_MEDIAMIX_PWRDNACKN … #define IMX8MP_HDMIMIX_PWRDNACKN … #define IMX8MP_HSIOMIX_PWRDNACKN … #define IMX8MP_VPUMIX_PWRDNACKN … #define IMX8MP_GPUMIX_PWRDNACKN … #define IMX8MP_MLMIX_PWRDNACKN … #define IMX8MP_AUDIOMIX_PWRDNACKN … #define IMX8MP_MEDIAMIX_PWRDNREQN … #define IMX8MP_HDMIMIX_PWRDNREQN … #define IMX8MP_HSIOMIX_PWRDNREQN … #define IMX8MP_VPUMIX_PWRDNREQN … #define IMX8MP_GPUMIX_PWRDNREQN … #define IMX8MP_MLMIX_PWRDNREQN … #define IMX8MP_AUDIOMIX_PWRDNREQN … /* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's * GPC_PGC memory map are incorrect, below offset * values are from design RTL. */ #define IMX7_PGC_MIPI … #define IMX7_PGC_PCIE … #define IMX7_PGC_USB_HSIC … #define IMX8M_PGC_MIPI … #define IMX8M_PGC_PCIE1 … #define IMX8M_PGC_OTG1 … #define IMX8M_PGC_OTG2 … #define IMX8M_PGC_DDR1 … #define IMX8M_PGC_GPU … #define IMX8M_PGC_VPU … #define IMX8M_PGC_DISP … #define IMX8M_PGC_MIPI_CSI1 … #define IMX8M_PGC_MIPI_CSI2 … #define IMX8M_PGC_PCIE2 … #define IMX8MM_PGC_MIPI … #define IMX8MM_PGC_PCIE … #define IMX8MM_PGC_OTG1 … #define IMX8MM_PGC_OTG2 … #define IMX8MM_PGC_DDR1 … #define IMX8MM_PGC_GPU2D … #define IMX8MM_PGC_GPUMIX … #define IMX8MM_PGC_VPUMIX … #define IMX8MM_PGC_GPU3D … #define IMX8MM_PGC_DISPMIX … #define IMX8MM_PGC_VPUG1 … #define IMX8MM_PGC_VPUG2 … #define IMX8MM_PGC_VPUH1 … #define IMX8MN_PGC_MIPI … #define IMX8MN_PGC_OTG1 … #define IMX8MN_PGC_DDR1 … #define IMX8MN_PGC_GPUMIX … #define IMX8MN_PGC_DISPMIX … #define IMX8MP_PGC_NOC … #define IMX8MP_PGC_MIPI1 … #define IMX8MP_PGC_PCIE … #define IMX8MP_PGC_USB1 … #define IMX8MP_PGC_USB2 … #define IMX8MP_PGC_MLMIX … #define IMX8MP_PGC_AUDIOMIX … #define IMX8MP_PGC_GPU2D … #define IMX8MP_PGC_GPUMIX … #define IMX8MP_PGC_VPUMIX … #define IMX8MP_PGC_GPU3D … #define IMX8MP_PGC_MEDIAMIX … #define IMX8MP_PGC_VPU_G1 … #define IMX8MP_PGC_VPU_G2 … #define IMX8MP_PGC_VPU_VC8000E … #define IMX8MP_PGC_HDMIMIX … #define IMX8MP_PGC_HDMI … #define IMX8MP_PGC_MIPI2 … #define IMX8MP_PGC_HSIOMIX … #define IMX8MP_PGC_MEDIA_ISP_DWP … #define IMX8MP_PGC_DDRMIX … #define GPC_PGC_CTRL(n) … #define GPC_PGC_SR(n) … #define GPC_PGC_CTRL_PCR … struct imx_pgc_regs { … }; struct imx_pgc_domain { … }; struct imx_pgc_domain_data { … }; static inline struct imx_pgc_domain * to_imx_pgc_domain(struct generic_pm_domain *genpd) { … } static int imx_pgc_power_up(struct generic_pm_domain *genpd) { … } static int imx_pgc_power_down(struct generic_pm_domain *genpd) { … } static const struct imx_pgc_domain imx7_pgc_domains[] = …; static const struct regmap_range imx7_yes_ranges[] = …; static const struct regmap_access_table imx7_access_table = …; static const struct imx_pgc_regs imx7_pgc_regs = …; static const struct imx_pgc_domain_data imx7_pgc_domain_data = …; static const struct imx_pgc_domain imx8m_pgc_domains[] = …; static const struct regmap_range imx8m_yes_ranges[] = …; static const struct regmap_access_table imx8m_access_table = …; static const struct imx_pgc_domain_data imx8m_pgc_domain_data = …; static const struct imx_pgc_domain imx8mm_pgc_domains[] = …; static const struct regmap_range imx8mm_yes_ranges[] = …; static const struct regmap_access_table imx8mm_access_table = …; static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = …; static const struct imx_pgc_domain imx8mp_pgc_domains[] = …; static const struct regmap_range imx8mp_yes_ranges[] = …; static const struct regmap_access_table imx8mp_access_table = …; static const struct imx_pgc_regs imx8mp_pgc_regs = …; static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = …; static const struct imx_pgc_domain imx8mn_pgc_domains[] = …; static const struct regmap_range imx8mn_yes_ranges[] = …; static const struct regmap_access_table imx8mn_access_table = …; static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = …; static int imx_pgc_domain_probe(struct platform_device *pdev) { … } static void imx_pgc_domain_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int imx_pgc_domain_suspend(struct device *dev) { … } static int imx_pgc_domain_resume(struct device *dev) { … } #endif static const struct dev_pm_ops imx_pgc_domain_pm_ops = …; static const struct platform_device_id imx_pgc_domain_id[] = …; static struct platform_driver imx_pgc_domain_driver = …; builtin_platform_driver(…) … static int imx_gpcv2_probe(struct platform_device *pdev) { … } static const struct of_device_id imx_gpcv2_dt_ids[] = …; static struct platform_driver imx_gpc_driver = …; builtin_platform_driver(…) …
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