/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2023, MediaTek Inc. * Copyright (c) 2023, BayLibre Inc. */ #ifndef __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__ #define __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__ /* * CSI1 and CSI2 are identical, and similar to CSI0. All CSIX macros are * applicable to the three PHYs. Where differences exist, they are denoted by * macro names using CSI0 and CSI1, the latter being applicable to CSI1 and * CSI2 alike. */ #define MIPI_RX_ANA00_CSIXA … #define RG_CSI0A_CPHY_EN … #define RG_CSIXA_EQ_PROTECT_EN … #define RG_CSIXA_BG_LPF_EN … #define RG_CSIXA_BG_CORE_EN … #define RG_CSIXA_DPHY_L0_CKMODE_EN … #define RG_CSIXA_DPHY_L0_CKSEL … #define RG_CSIXA_DPHY_L1_CKMODE_EN … #define RG_CSIXA_DPHY_L1_CKSEL … #define RG_CSIXA_DPHY_L2_CKMODE_EN … #define RG_CSIXA_DPHY_L2_CKSEL … #define MIPI_RX_ANA18_CSIXA … #define RG_CSI0A_L0_T0AB_EQ_IS … #define RG_CSI0A_L0_T0AB_EQ_BW … #define RG_CSI0A_L1_T1AB_EQ_IS … #define RG_CSI0A_L1_T1AB_EQ_BW … #define RG_CSI0A_L2_T1BC_EQ_IS … #define RG_CSI0A_L2_T1BC_EQ_BW … #define RG_CSI1A_L0_EQ_IS … #define RG_CSI1A_L0_EQ_BW … #define RG_CSI1A_L1_EQ_IS … #define RG_CSI1A_L1_EQ_BW … #define RG_CSI1A_L2_EQ_IS … #define RG_CSI1A_L2_EQ_BW … #define MIPI_RX_ANA1C_CSIXA … #define MIPI_RX_ANA20_CSI0A … #define MIPI_RX_ANA24_CSIXA … #define RG_CSIXA_RESERVE … #define MIPI_RX_ANA40_CSIXA … #define RG_CSIXA_CPHY_FMCK_SEL … #define RG_CSIXA_ASYNC_OPTION … #define RG_CSIXA_CPHY_SPARE … #define MIPI_RX_WRAPPER80_CSIXA … #define CSR_CSI_RST_MODE … #define MIPI_RX_ANAA8_CSIXA … #define RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT … #define RG_CSIXA_DPHY_L1_BYTECK_INVERT … #define RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT … #endif
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