/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2018 ROHM Semiconductors */ #ifndef __LINUX_MFD_BD718XX_H__ #define __LINUX_MFD_BD718XX_H__ #include <linux/mfd/rohm-generic.h> #include <linux/regmap.h> enum { … }; /* Common voltage configurations */ #define BD718XX_DVS_BUCK_VOLTAGE_NUM … #define BD718XX_4TH_NODVS_BUCK_VOLTAGE_NUM … #define BD718XX_LDO1_VOLTAGE_NUM … #define BD718XX_LDO2_VOLTAGE_NUM … #define BD718XX_LDO3_VOLTAGE_NUM … #define BD718XX_LDO4_VOLTAGE_NUM … #define BD718XX_LDO6_VOLTAGE_NUM … /* BD71837 specific voltage configurations */ #define BD71837_BUCK5_VOLTAGE_NUM … #define BD71837_BUCK6_VOLTAGE_NUM … #define BD71837_BUCK7_VOLTAGE_NUM … #define BD71837_LDO5_VOLTAGE_NUM … #define BD71837_LDO7_VOLTAGE_NUM … /* BD71847 specific voltage configurations */ #define BD71847_BUCK3_VOLTAGE_NUM … #define BD71847_BUCK4_VOLTAGE_NUM … #define BD71847_LDO5_VOLTAGE_NUM … /* Registers specific to BD71837 */ enum { … }; /* Registers common for BD71837 and BD71847 */ enum { … }; #define REGLOCK_PWRSEQ … #define REGLOCK_VREG … /* Generic BUCK control masks */ #define BD718XX_BUCK_SEL … #define BD718XX_BUCK_EN … #define BD718XX_BUCK_RUN_ON … /* Generic LDO masks */ #define BD718XX_LDO_SEL … #define BD718XX_LDO_EN … /* BD71837 BUCK ramp rate CTRL reg bits */ #define BUCK_RAMPRATE_MASK … #define BUCK_RAMPRATE_10P00MV … #define BUCK_RAMPRATE_5P00MV … #define BUCK_RAMPRATE_2P50MV … #define BUCK_RAMPRATE_1P25MV … #define DVS_BUCK_RUN_MASK … #define DVS_BUCK_SUSP_MASK … #define DVS_BUCK_IDLE_MASK … #define BD718XX_1ST_NODVS_BUCK_MASK … #define BD718XX_3RD_NODVS_BUCK_MASK … #define BD718XX_4TH_NODVS_BUCK_MASK … #define BD71847_BUCK3_MASK … #define BD71847_BUCK3_RANGE_MASK … #define BD71847_BUCK4_MASK … #define BD71847_BUCK4_RANGE_MASK … #define BD71837_BUCK5_MASK … #define BD71837_BUCK5_RANGE_MASK … #define BD71837_BUCK6_MASK … #define BD718XX_LDO1_MASK … #define BD718XX_LDO1_RANGE_MASK … #define BD718XX_LDO2_MASK … #define BD718XX_LDO3_MASK … #define BD718XX_LDO4_MASK … #define BD718XX_LDO6_MASK … #define BD71837_LDO5_MASK … #define BD71847_LDO5_MASK … #define BD71847_LDO5_RANGE_MASK … #define BD71837_LDO7_MASK … /* BD718XX Voltage monitoring masks */ #define BD718XX_BUCK1_VRMON80 … #define BD718XX_BUCK1_VRMON130 … #define BD718XX_BUCK2_VRMON80 … #define BD718XX_BUCK2_VRMON130 … #define BD718XX_1ST_NODVS_BUCK_VRMON80 … #define BD718XX_1ST_NODVS_BUCK_VRMON130 … #define BD718XX_2ND_NODVS_BUCK_VRMON80 … #define BD718XX_2ND_NODVS_BUCK_VRMON130 … #define BD718XX_3RD_NODVS_BUCK_VRMON80 … #define BD718XX_3RD_NODVS_BUCK_VRMON130 … #define BD718XX_4TH_NODVS_BUCK_VRMON80 … #define BD718XX_4TH_NODVS_BUCK_VRMON130 … #define BD718XX_LDO1_VRMON80 … #define BD718XX_LDO2_VRMON80 … #define BD718XX_LDO3_VRMON80 … #define BD718XX_LDO4_VRMON80 … #define BD718XX_LDO5_VRMON80 … #define BD718XX_LDO6_VRMON80 … /* BD71837 specific voltage monitoring masks */ #define BD71837_BUCK3_VRMON80 … #define BD71837_BUCK3_VRMON130 … #define BD71837_BUCK4_VRMON80 … #define BD71837_BUCK4_VRMON130 … #define BD71837_LDO7_VRMON80 … /* BD718XX_REG_IRQ bits */ #define IRQ_SWRST … #define IRQ_PWRON_S … #define IRQ_PWRON_L … #define IRQ_PWRON … #define IRQ_WDOG … #define IRQ_ON_REQ … #define IRQ_STBY_REQ … /* ROHM BD718XX irqs */ enum { … }; /* ROHM BD718XX interrupt masks */ #define BD718XX_INT_SWRST_MASK … #define BD718XX_INT_PWRBTN_S_MASK … #define BD718XX_INT_PWRBTN_L_MASK … #define BD718XX_INT_PWRBTN_MASK … #define BD718XX_INT_WDOG_MASK … #define BD718XX_INT_ON_REQ_MASK … #define BD718XX_INT_STBY_REQ_MASK … /* Register write induced reset settings */ /* * Even though the bit zero is not SWRESET type we still want to write zero * to it when changing type. Bit zero is 'SWRESET' trigger bit and if we * write 1 to it we will trigger the action. So always write 0 to it when * changning SWRESET action - no matter what we read from it. */ #define BD718XX_SWRESET_TYPE_MASK … #define BD718XX_SWRESET_TYPE_DISABLED … #define BD718XX_SWRESET_TYPE_COLD … #define BD718XX_SWRESET_TYPE_WARM … #define BD718XX_SWRESET_RESET_MASK … #define BD718XX_SWRESET_RESET … /* Poweroff state transition conditions */ #define BD718XX_ON_REQ_POWEROFF_MASK … #define BD718XX_SWRESET_POWEROFF_MASK … #define BD718XX_WDOG_POWEROFF_MASK … #define BD718XX_KEY_L_POWEROFF_MASK … #define BD718XX_POWOFF_TO_SNVS … #define BD718XX_POWOFF_TO_RDY … #define BD718XX_POWOFF_TIME_MASK … enum { … }; /* Poweron sequence state transition conditions */ #define BD718XX_RDY_TO_SNVS_MASK … #define BD718XX_SNVS_TO_RUN_MASK … #define BD718XX_PWR_TRIG_KEY_L … #define BD718XX_PWR_TRIG_KEY_S … #define BD718XX_PWR_TRIG_PMIC_ON … #define BD718XX_PWR_TRIG_VSYS_UVLO … #define BD718XX_RDY_TO_SNVS_SIFT … #define BD718XX_SNVS_TO_RUN_SIFT … #define BD718XX_PWRBTN_PRESS_DURATION_MASK … /* Timeout value for detecting short press */ enum { … }; /* Timeout value for detecting LONG press */ enum { … }; #endif /* __LINUX_MFD_BD718XX_H__ */
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