/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2021 ROHM Semiconductors */ #ifndef __LINUX_MFD_BD957X_H__ #define __LINUX_MFD_BD957X_H__ enum { … }; /* * The BD9576 has own IRQ 'blocks' for: * - I2C/thermal, * - Over voltage protection * - Short-circuit protection * - Over current protection * - Over voltage detection * - Under voltage detection * - Under voltage protection * - 'system interrupt'. * * Each of the blocks have a status register giving more accurate IRQ source * information - for example which of the regulators have over-voltage. * * On top of this, there is "main IRQ" status register where each bit indicates * which of sub-blocks have active IRQs. Fine. That would fit regmap-irq main * status handling. Except that: * - Only some sub-IRQs can be masked. * - The IRQ informs us about fault-condition, not when fault state changes. * The IRQ line it is kept asserted until the detected condition is acked * AND cleared in HW. This is annoying for IRQs like the one informing high * temperature because if IRQ is not disabled it keeps the CPU in IRQ * handling loop. * * For now we do just use the main-IRQ register as source for our IRQ * information and bind the regmap-irq to this. We leave fine-grained sub-IRQ * register handling to handlers in sub-devices. The regulator driver shall * read which regulators are source for problem - or if the detected error is * regulator temperature error. The sub-drivers do also handle masking of "sub- * IRQs" if this is supported/needed. * * To overcome the problem with HW keeping IRQ asserted we do call * disable_irq_nosync() from sub-device handler and add a delayed work to * re-enable IRQ roughly 1 second later. This should keep our CPU out of * busy-loop. */ #define IRQS_SILENT_MS … enum { … }; #define BD957X_REG_SMRB_ASSERT … #define BD957X_REG_PMIC_INTERNAL_STAT … #define BD957X_REG_INT_THERM_STAT … #define BD957X_REG_INT_THERM_MASK … #define BD957X_REG_INT_OVP_STAT … #define BD957X_REG_INT_SCP_STAT … #define BD957X_REG_INT_OCP_STAT … #define BD957X_REG_INT_OVD_STAT … #define BD957X_REG_INT_UVD_STAT … #define BD957X_REG_INT_UVP_STAT … #define BD957X_REG_INT_SYS_STAT … #define BD957X_REG_INT_SYS_MASK … #define BD957X_REG_INT_MAIN_STAT … #define BD957X_REG_INT_MAIN_MASK … #define UVD_IRQ_VALID_MASK … #define OVD_IRQ_VALID_MASK … #define BD957X_MASK_INT_MAIN_THERM … #define BD957X_MASK_INT_MAIN_OVP … #define BD957X_MASK_INT_MAIN_SCP … #define BD957X_MASK_INT_MAIN_OCP … #define BD957X_MASK_INT_MAIN_OVD … #define BD957X_MASK_INT_MAIN_UVD … #define BD957X_MASK_INT_MAIN_UVP … #define BD957X_MASK_INT_MAIN_SYS … #define BD957X_MASK_INT_ALL … #define BD957X_REG_WDT_CONF … #define BD957X_REG_POW_TRIGGER1 … #define BD957X_REG_POW_TRIGGER2 … #define BD957X_REG_POW_TRIGGER3 … #define BD957X_REG_POW_TRIGGER4 … #define BD957X_REG_POW_TRIGGERL1 … #define BD957X_REG_POW_TRIGGERS1 … #define BD957X_REGULATOR_EN_MASK … #define BD957X_REGULATOR_DIS_VAL … #define BD957X_VSEL_REG_MASK … #define BD957X_MASK_VOUT1_TUNE … #define BD957X_MASK_VOUT2_TUNE … #define BD957X_MASK_VOUT3_TUNE … #define BD957X_MASK_VOUT4_TUNE … #define BD957X_MASK_VOUTL1_TUNE … #define BD957X_REG_VOUT1_TUNE … #define BD957X_REG_VOUT2_TUNE … #define BD957X_REG_VOUT3_TUNE … #define BD957X_REG_VOUT4_TUNE … #define BD957X_REG_VOUTL1_TUNE … #define BD9576_REG_VOUT1_OVD … #define BD9576_REG_VOUT1_UVD … #define BD9576_REG_VOUT2_OVD … #define BD9576_REG_VOUT2_UVD … #define BD9576_REG_VOUT3_OVD … #define BD9576_REG_VOUT3_UVD … #define BD9576_REG_VOUT4_OVD … #define BD9576_REG_VOUT4_UVD … #define BD9576_REG_VOUTL1_OVD … #define BD9576_REG_VOUTL1_UVD … #define BD9576_MASK_XVD … #define BD9576_REG_VOUT1S_OCW … #define BD9576_REG_VOUT1S_OCP … #define BD9576_MASK_VOUT1S_OCW … #define BD9576_MASK_VOUT1S_OCP … #define BD957X_MAX_REGISTER … #endif
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