// SPDX-License-Identifier: GPL-2.0-only /* * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU). * * Copyright (C) 2015 Joachim Eastwood <[email protected]> */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/reboot.h> #include <linux/reset-controller.h> #include <linux/spinlock.h> /* LPC18xx RGU registers */ #define LPC18XX_RGU_CTRL0 … #define LPC18XX_RGU_CTRL1 … #define LPC18XX_RGU_ACTIVE_STATUS0 … #define LPC18XX_RGU_ACTIVE_STATUS1 … #define LPC18XX_RGU_RESETS_PER_REG … /* Internal reset outputs */ #define LPC18XX_RGU_CORE_RST … #define LPC43XX_RGU_M0SUB_RST … #define LPC43XX_RGU_M0APP_RST … struct lpc18xx_rgu_data { … }; #define to_rgu_data(p) … static int lpc18xx_rgu_restart(struct notifier_block *nb, unsigned long mode, void *cmd) { … } /* * The LPC18xx RGU has mostly self-deasserting resets except for the * two reset lines going to the internal Cortex-M0 cores. * * To prevent the M0 core resets from accidentally getting deasserted * status register must be check and bits in control register set to * preserve the state. */ static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev, unsigned long id, bool set) { … } static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev, unsigned long id) { … } /* Only M0 cores require explicit reset deassert */ static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev, unsigned long id) { … } static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev, unsigned long id) { … } static const struct reset_control_ops lpc18xx_rgu_ops = …; static int lpc18xx_rgu_probe(struct platform_device *pdev) { … } static const struct of_device_id lpc18xx_rgu_match[] = …; static struct platform_driver lpc18xx_rgu_driver = …; builtin_platform_driver(…) …;
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