/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2019 Sean Anderson <[email protected]> * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ #ifndef RESET_K210_SYSCTL_H #define RESET_K210_SYSCTL_H /* * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. * Taken from Kendryte SDK (kendryte-standalone-sdk). */ #define K210_RST_ROM … #define K210_RST_DMA … #define K210_RST_AI … #define K210_RST_DVP … #define K210_RST_FFT … #define K210_RST_GPIO … #define K210_RST_SPI0 … #define K210_RST_SPI1 … #define K210_RST_SPI2 … #define K210_RST_SPI3 … #define K210_RST_I2S0 … #define K210_RST_I2S1 … #define K210_RST_I2S2 … #define K210_RST_I2C0 … #define K210_RST_I2C1 … #define K210_RST_I2C2 … #define K210_RST_UART1 … #define K210_RST_UART2 … #define K210_RST_UART3 … #define K210_RST_AES … #define K210_RST_FPIOA … #define K210_RST_TIMER0 … #define K210_RST_TIMER1 … #define K210_RST_TIMER2 … #define K210_RST_WDT0 … #define K210_RST_WDT1 … #define K210_RST_SHA … #define K210_RST_RTC … #endif /* RESET_K210_SYSCTL_H */
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